Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset

General Description The SSTV16859 is a dual output 13-bit register designed for use with 184 and 232 pin DDR-1 memory modules. The device has a differential input clock, SSTL-2 compatible data inputs and a LVCMOS compatible RESET input. The device has been designed to meet the JEDEC DDR module re

2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM

DESCRIPTION The SSTV16859 is a 13-bit to 26-bit SSTL_2 registered driver with differential clock inputs, designed to operate between 2.3 V and 2.7 V. All inputs are compatible with the JEDEC standard for SSTL_2 with VREF normally at 0.5*VDD, except the LVCMOS reset (RESET) input. All outputs are

13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL 2 INPUTS AND OUTPUTS

文件：166.62 Kbytes Page：10 Pages

3-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL 2 INPUTS AND OUTPUTS

文件：663.36 Kbytes Page：15 Pages

Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset

2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM

DESCRIPTION The SSTV16859 is a 13-bit to 26-bit SSTL_2 registered driver with differential clock inputs, designed to operate between 2.3 V and 2.7 V. All inputs are compatible with the JEDEC standard for SSTL_2 with VREF normally at 0.5*VDD, except the LVCMOS reset (RESET) input. All outputs are

2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM

DESCRIPTION The SSTV16859 is a 13-bit to 26-bit SSTL_2 registered driver with differential clock inputs, designed to operate between 2.3 V and 2.7 V. All inputs are compatible with the JEDEC standard for SSTL_2 with VREF normally at 0.5*VDD, except the LVCMOS reset (RESET) input. All outputs are

2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM

DESCRIPTION The SSTV16859 is a 13-bit to 26-bit SSTL_2 registered driver with differential clock inputs, designed to operate between 2.3 V and 2.7 V. All inputs are compatible with the JEDEC standard for SSTL_2 with VREF normally at 0.5*VDD, except the LVCMOS reset (RESET) input. All outputs are

Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset

General Description The SSTV16859 is a dual output 13-bit register designed for use with 184 and 232 pin DDR-1 memory modules. The device has a differential input clock, SSTL-2 compatible data inputs and a LVCMOS compatible RESET input. The device has been designed to meet the JEDEC DDR module re

Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset

General Description The SSTV16859 is a dual output 13-bit register designed for use with 184 and 232 pin DDR-1 memory modules. The device has a differential input clock, SSTL-2 compatible data inputs and a LVCMOS compatible RESET input. The device has been designed to meet the JEDEC DDR module re

2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM

封装/外壳：56-VFQFN 裸露焊盘 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC REG BUFFER 13-26BIT 56-HVQFN 集成电路（IC） 专用逻辑器件

封装/外壳：56-VFQFN 裸露焊盘 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC REG BUFFER 26BIT 56HVQFN 集成电路（IC） 专用逻辑器件

SSTV16859DGG

DDR 13-Bit to 26-Bit Registered Buffer

General Description The 13-bit-to-26-bit ICSSSTV16859 is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/O levels, except for the LVCMOS RESET# input. Product Features: • Differential clock signals • Meets SSTL_2 signal data • Supports SSTL_2 class II specification

DDR 13-Bit to 26-Bit Registered BuDDR

Recommended Applications: • DDR Memory Modules • Provides complete DDR DIMM logic solution with ICS93V857 or ICS95V857 • SSTL_2 compatible data registers Product Features: • Differential clock signals • Meets SSTL_2 signal data • Supports SSTL_2 class II specifications on outputs • Low-vo

Asymmetric beam for wall washing

文件：4.29423 Mbytes Page：6 Pages

DDR 13-Bit to 26-Bit Registered Buffer

文件：97.15 Kbytes Page：8 Pages

DDR 13-Bit to 26-Bit Registered Buffer

文件：95.77 Kbytes Page：8 Pages