SURFACE MOUNT SUPER FAST RECTIFIERS

PRV : 50 - 1000 Volts Io : 2.5 Amperes FEATURES : * High current capability * High surge current capability * High reliability * Low reverse current * Low forward voltage drop * Super fast recovery time * Pb / RoHS Free

SURFACE MOUNT SUPER FAST RECTIFIERS

PRV : 50 - 1000 Volts Io : 2.5 Amperes FEATURES : * High current capability * High surge current capability * High reliability * Low reverse current * Low forward voltage drop * Super fast recovery time * Pb / RoHS Free

Rectifiers: Super Fast Recovery

DDR3 Register + PLL

This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.25V, 1.35V and 1.5V VDD operation • DDR3-800/1066/1333/1600/1866/2133 rate\n• Phase Lock Loop clock driver for buffering one differential clock pair (CK and CK) and distributing to four differential outputs\n• Checks priority on DIMM-independent data inputs\n• Supports CKE Power Down operation modes\n• RESET input disables different;

LOW POWER DDR3 Register + PLL

This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.25V, 1.35V and 1.5V VDD operation • DDR3-800/1066/1333/1600/1866/2133 rate\n• 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs support stacked DDR3 RDIMMs\n• Phase Lock Loop clock driver for buffering one differential clock pair (CK and CK) and distributing to four differential outputs\n• Supports LVCMOS switching levels on the;

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT

Features • Pinout optimizes DDR3 RDIMM PCB layout • DDR3-800/1066/1333/1600/1866/2133 rate • 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs support stacked DDR3 RDIMMs • Phase Lock Loop clock driver for buffering one differential clock pair (CK and CK) and distributing to four different

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT

Features • Pinout optimizes DDR3 RDIMM PCB layout • DDR3-800/1066/1333/1600/1866/2133 rate • 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs support stacked DDR3 RDIMMs • Phase Lock Loop clock driver for buffering one differential clock pair (CK and CK) and distributing to four different

Pinout optimizes DDR3 RDIMM PCB layout

文件：1.37612 Mbytes Page：73 Pages

封装/外壳：176-TFBGA 包装：卷带（TR） 描述：IC REGISTERING CLK DRIVER 176BGA 集成电路（IC） 应用特定时钟/定时

Pinout optimizes DDR3 RDIMM PCB layout

文件：1.68385 Mbytes Page：75 Pages

封装/外壳：176-TFBGA 包装：卷带（TR） 描述：IC REGISTERING CLK DRIVER 176BGA 集成电路（IC） 应用特定时钟/定时

Pinout optimizes DDR3 RDIMM PCB layout

文件：1.3656 Mbytes Page：75 Pages