DDR3 Register + PLL

This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.35V and 1.5V VDD operationwith parity is designed for 1.35V and 1.5V VDD operation • DDR3-800/1066/1333/1600 rate\n• 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs support stacked DDR3 RDIMMs\n• Phase Lock Loop clock driver for buffering one differential clock pair (CK and CK) and distributing to four differential outputs\n• Supports LVCMOS switching levels on the RESET and;

Pinout optimizes DDR3 RDIMM PCB layout

文件：1.37612 Mbytes Page：73 Pages

封装/外壳：176-TFBGA 包装：托盘 描述：IC REGISTERING CLK DRIVER 176BGA 集成电路（IC） 应用特定时钟/定时

封装/外壳：176-TFBGA 包装：卷带（TR） 描述：IC REGISTERING CLK DRIVER 176BGA 集成电路（IC） 应用特定时钟/定时

TERMINAL, RING TOMGUE, BUDGET

文件：82.56 Kbytes Page：1 Pages

1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT

文件：1.37611 Mbytes Page：73 Pages