25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS

Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR-II DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption Output Edge-Control Circuitry Minimizes S

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

文件：139.25 Kbytes Page：12 Pages

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

文件：179.41 Kbytes Page：12 Pages

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

文件：139.25 Kbytes Page：12 Pages