3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

Members of the Texas Instruments (TIE) Broad Family of Testability Products Supporting IEEE Std 1149.1-1990 (JTAG) Test Access Port (TAP) and Boundary-Scan Architecture Extend Scan Access From Board Level to Higher Levels of System Integration Promote Reuse of Lower-Level Chip/Board) Tests

3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 JTAG TAP TRANSCEIVERS

文件：717.8 Kbytes Page：44 Pages

封装/外壳：24-SOIC（0.295"，7.50mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC 10-BIT SCAN PORT XCVR 24-SOIC 集成电路（IC） 专用逻辑器件

3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 JTAG TAP TRANSCEIVERS

文件：717.8 Kbytes Page：44 Pages

3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

文件：603.55 Kbytes Page：41 Pages

3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

Members of the Texas Instruments (TIE) Broad Family of Testability Products Supporting IEEE Std 1149.1-1990 (JTAG) Test Access Port (TAP) and Boundary-Scan Architecture Extend Scan Access From Board Level to Higher Levels of System Integration Promote Reuse of Lower-Level Chip/Board) Tests

3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 JTAG TAP TRANSCEIVERS

文件：717.8 Kbytes Page：44 Pages

封装/外壳：24-SOIC（0.295"，7.50mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC 10-BIT SCAN PORT XCVR 24-SOIC 集成电路（IC） 专用逻辑器件