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SN74LVC74ADR价格
参考价格：￥0.4791
型号：SN74LVC74ADR 品牌：TI 备注：这里有SN74LVC74ADR多少钱，2025年最近7天走势，今日出价，今日竞价，SN74LVC74ADR批发/采购报价，SN74LVC74ADR行情走势销售排行榜，SN74LVC74ADR报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
SN74LVC74ADR | SNx4LVC74A Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 1 Features • Operate from 1.65V to 3.6V • Inputs accept voltages to 5.5V • Maximum tpd of 5.2ns at 3.3V • Typical VOLP (output ground bounce) 2V at VCC = 3.3V, TA = 25°C • Latch-up performance exceeds 250mA per JESD 17 | TI 德州仪器 |   | |
SN74LVC74ADR | SNx4LVC74A Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 1 Features • Operate from 1.65V to 3.6V • Inputs accept voltages to 5.5V • Maximum tpd of 5.2ns at 3.3V • Typical VOLP (output ground bounce) 2V at VCC = 3.3V, TA = 25°C • Latch-up performance exceeds 250mA per JESD 17 | TI 德州仪器 | | |
SN74LVC74ADR | SNx4LVC74A Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 1 Features • Operate from 1.65V to 3.6V • Inputs accept voltages to 5.5V • Maximum tpd of 5.2ns at 3.3V • Typical VOLP (output ground bounce) 2V at VCC = 3.3V, TA = 25°C • Latch-up performance exceeds 250mA per JESD 17 | TI 德州仪器 | | |
SN74LVC74ADR | DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET 文件：516.539 Kbytes Page：17 Pages | TI 德州仪器 | | |
SN74LVC74ADR | DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET 文件：814.84 Kbytes Page：19 Pages | TI 德州仪器 | | |
SN74LVC74ADR | DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET 文件：661.44 Kbytes Page：19 Pages | TI 德州仪器 | | |
SN74LVC74ADR | DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET 文件：1.2074 Mbytes Page：27 Pages | TI 德州仪器 | | |
SN74LVC74ADR | 封装/外壳：14-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE DUAL 1BIT 14SOIC 集成电路（IC） 触发器 | TI 德州仪器 | | |
SNx4LVC74A Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 1 Features • Operate from 1.65V to 3.6V • Inputs accept voltages to 5.5V • Maximum tpd of 5.2ns at 3.3V • Typical VOLP (output ground bounce) 2V at VCC = 3.3V, TA = 25°C • Latch-up performance exceeds 250mA per JESD 17 | TI 德州仪器 | | ||
SNx4LVC74A Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 1 Features • Operate from 1.65V to 3.6V • Inputs accept voltages to 5.5V • Maximum tpd of 5.2ns at 3.3V • Typical VOLP (output ground bounce) 2V at VCC = 3.3V, TA = 25°C • Latch-up performance exceeds 250mA per JESD 17 | TI 德州仪器 | | ||
SNx4LVC74A Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 1 Features • Operate from 1.65V to 3.6V • Inputs accept voltages to 5.5V • Maximum tpd of 5.2ns at 3.3V • Typical VOLP (output ground bounce) 2V at VCC = 3.3V, TA = 25°C • Latch-up performance exceeds 250mA per JESD 17 | TI 德州仪器 | | ||
SNx4LVC74A Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 1 Features • Operate from 1.65V to 3.6V • Inputs accept voltages to 5.5V • Maximum tpd of 5.2ns at 3.3V • Typical VOLP (output ground bounce) 2V at VCC = 3.3V, TA = 25°C • Latch-up performance exceeds 250mA per JESD 17 | TI 德州仪器 | | ||
SNx4LVC74A Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 1 Features • Operate from 1.65V to 3.6V • Inputs accept voltages to 5.5V • Maximum tpd of 5.2ns at 3.3V • Typical VOLP (output ground bounce) 2V at VCC = 3.3V, TA = 25°C • Latch-up performance exceeds 250mA per JESD 17 | TI 德州仪器 | | ||
SNx4LVC74A Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 1 Features • Operate from 1.65V to 3.6V • Inputs accept voltages to 5.5V • Maximum tpd of 5.2ns at 3.3V • Typical VOLP (output ground bounce) 2V at VCC = 3.3V, TA = 25°C • Latch-up performance exceeds 250mA per JESD 17 | TI 德州仪器 | | ||
SN74LVC74A-Q1 Automotive Dual Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset 1 Features • Qualified for automotive applications • ESD protection exceeds 2000V per MIL-STD-883, Method 3015 • Operates from 2V to 3.6V • Inputs accept voltages to 5.5V • Max tpd of 5.2ns at 3.3V • Typical VOLP (output ground bounce) | TI 德州仪器 | | ||
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET 文件：516.539 Kbytes Page：17 Pages | TI 德州仪器 | | ||
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET 文件：1.2074 Mbytes Page：27 Pages | TI 德州仪器 | | ||
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET 文件：814.84 Kbytes Page：19 Pages | TI 德州仪器 | | ||
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET 文件：661.44 Kbytes Page：19 Pages | TI 德州仪器 | | ||
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET 文件：661.44 Kbytes Page：19 Pages | TI 德州仪器 | | ||
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET 文件：814.84 Kbytes Page：19 Pages | TI 德州仪器 | | ||
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET 文件：1.2074 Mbytes Page：27 Pages | TI 德州仪器 | | ||
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET 文件：516.539 Kbytes Page：17 Pages | TI 德州仪器 | | ||
封装/外壳：14-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：管件 描述：IC FF D-TYPE DUAL 1BIT 14SOIC 集成电路（IC） 触发器 | TI 德州仪器 | | ||
Dual D-type flip-flop with set and reset; positive-edge trigger DESCRIPTION The 74LVC74A is a high-performance, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES •Wide supply voltage range of 1.2 V to 3.6 V •In accordance with JEDEC standard no. 8-1A. •Inputs accept voltages up to 5.5 V •CMOS low power c | Philips 飞利浦 | | ||
Dual D-type flip-flop with set and reset; positive-edge trigger 1. General description The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input | NEXPERIA 安世 | | ||
Dual D-type flip-flop with set and reset; positive-edge trigger | ETC 知名厂家 | ETC | | |
Dual D-type flip-flop with set and reset; positive-edge trigger | ETC 知名厂家 | ETC | | |
Dual D-type flip-flop with set and reset; positive-edge trigger 1. General description The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input | NEXPERIA 安世 | |
SN74LVC74ADR产品属性
- 类型
描述
- 型号
SN74LVC74ADR
- 功能描述
触发器 Tri-State Dual
- RoHS
否
- 制造商
Texas Instruments
- 电路数量
2
- 逻辑系列
SN74
- 逻辑类型
D-Type Flip-Flop
- 极性
Inverting, Non-Inverting
- 输入类型
CMOS
- 传播延迟时间
4.4 ns
- 高电平输出电流
- 16 mA
- 低电平输出电流
16 mA
- 电源电压-最大
5.5 V
- 最大工作温度
+ 85 C
- 安装风格
SMD/SMT
- 封装/箱体
X2SON-8
- 封装
Reel
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
TI |
SOP-14 |
68500 |
一级代理 原装正品假一罚十价格优势长期供货 |
||||
TI/德州仪器 |
24+ |
SOP14 |
521301 |
只供应原装正品 欢迎询价 |
|||
TI |
18+ |
SOP14 |
85600 |
保证进口原装可开17%增值税发票 |
|||
TI |
2016+ |
SOP14 |
2980 |
公司只做原装,假一罚十,可开17%增值税发票! |
|||
TI/德州仪器 |
24+ |
SOP14 |
66000 |
全新原装现货特价销售,欢迎来电查询 |
|||
TI |
24+ |
SOP14 |
39500 |
进口原装现货 支持实单价优 |
|||
TI |
22+ |
14SOIC |
9000 |
原厂渠道,现货配单 |
|||
TI |
24+/25+ |
2069 |
原装正品现货库存价优 |
||||
TI/德州仪器 |
2450+ |
SOP |
8850 |
只做原装正品假一赔十为客户做到零风险!! |
|||
TI/德州仪器 |
310 |
SOP-14 |
830 |
原装现货 价格优势 |
SN74LVC74ADR芯片相关品牌
SN74LVC74ADR规格书下载地址
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- SN74LVC74APWTG4
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- SN74LVC74AMPWREP
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- SN74LVC74ADG4
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- SN74LVC652APWR
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- SN74LVC
- SN74LV
- SN74LS
- SN74L71
- SN74L44
- SN74L43
- SN74L42
- SN74HC
- SN74H87
- SN74H78
- SN74H74
- SN74H62
- SN74H61
- SN74H60
- SN74H00
- SN74F86
- SN74F74
- SN74F51
- SN74F38
- SN74F37
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DdatasheetPDF页码索引
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