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74LVC74AD价格

参考价格:¥0.3560

型号:74LVC74AD,112 品牌:NXP 备注:这里有74LVC74AD多少钱,2026年最近7天走势,今日出价,今日竞价,74LVC74AD批发/采购报价,74LVC74AD行情走势销售排行榜,74LVC74AD报价。
型号 功能描述 生产厂家 企业 LOGO 操作
74LVC74AD

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LVC74A is a high-performance, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES •Wide supply voltage range of 1.2 V to 3.6 V •In accordance with JEDEC standard no. 8-1A. •Inputs accept voltages up to 5.5 V •CMOS low power c

PHILIPS

飞利浦

74LVC74AD

Dual D-type flip-flop with set and reset; positive-edge trigger

ETC

知名厂家

74LVC74AD

Dual D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input

NEXPERIA

安世

74LVC74AD

Dual D-type flip-flop with set and reset; positive-edge trigger

The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs.\n The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the dat • 5 V tolerant inputs for interlacing with 5 V logic\n• Wide supply voltage range from 1.2 V to 3.6 V\n• CMOS low power consumption\n• Direct interface with TTL levels\n• Complies with JEDEC standard:• JESD8-7A (1.65 V to 1.95 V)\n• JESD8-5A (2.3 V to 2.7 V)\n• JESD8-C/JESD36 (2.7 V to 3.6 V)\n\n• E;

NEXPERIA

安世

Dual D-type flip-flop with set and reset; positive-edge trigger

The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs.\n The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the dat • 5 V tolerant inputs for interlacing with 5 V logic\n• Wide supply voltage range from 1.2 V to 3.6 V\n• CMOS low power consumption\n• Direct interface with TTL levels\n• Complies with JEDEC standard:• JESD8-7A (1.65 V to 1.95 V)\n• JESD8-5A (2.3 V to 2.7 V)\n• JESD8-C/JESD36 (2.7 V to 3.6 V)\n\n• E;

NEXPERIA

安世

Dual D-type flip-flop with set and reset; positive-edge trigger

ETC

知名厂家

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LVC74A is a high-performance, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES •Wide supply voltage range of 1.2 V to 3.6 V •In accordance with JEDEC standard no. 8-1A. •Inputs accept voltages up to 5.5 V •CMOS low power c

PHILIPS

飞利浦

Dual D-type flip-flop with set and reset; positive-edge trigger

General description The 74LVC74A-Q100 is a dual edge triggered D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock in

NEXPERIA

安世

Dual D-type flip-flop with set and reset; positive-edge trigger

The 74LVC74A-Q100 is a dual edge triggered D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs.\n The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• 5 V tolerant inputs for interlacing with 5 V logic\n• Wide supply voltage range from 1.2 V to 3.6 V\n• CMOS low power consumption\n• Direct interface with TTL lev;

NEXPERIA

安世

封装/外壳:14-SOIC(0.154",3.90mm 宽) 功能:设置(预设)和复位 包装:卷带(TR)剪切带(CT)Digi-Reel® 得捷定制卷带 描述:IC FF D-TYPE DUAL 1BIT 14SO 集成电路(IC) 触发器

ETC

知名厂家

封装/外壳:14-SOIC(0.154",3.90mm 宽) 功能:设置(预设)和复位 包装:管件 描述:IC FF D-TYPE DUAL 1BIT 14SO 集成电路(IC) 触发器

ETC

知名厂家

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LVC74A is a high-performance, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES •Wide supply voltage range of 1.2 V to 3.6 V •In accordance with JEDEC standard no. 8-1A. •Inputs accept voltages up to 5.5 V •CMOS low power c

PHILIPS

飞利浦

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LVC74A is a high-performance, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES •Wide supply voltage range of 1.2 V to 3.6 V •In accordance with JEDEC standard no. 8-1A. •Inputs accept voltages up to 5.5 V •CMOS low power c

PHILIPS

飞利浦

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LVC74A is a high-performance, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES •Wide supply voltage range of 1.2 V to 3.6 V •In accordance with JEDEC standard no. 8-1A. •Inputs accept voltages up to 5.5 V •CMOS low power c

PHILIPS

飞利浦

74LVC74AD产品属性

  • 类型

    描述

  • VCC (V):

    1.2 - 3.6

  • Logic switching levels:

    CMOS/LVTTL

  • Output drive capability (mA):

    ± 24

  • tpd (ns):

    2.5

  • fmax (MHz):

    250

  • Power dissipation considerations:

    low

  • Tamb (°C):

    -40~125

  • Rth(j-a) (K/W):

    109

  • Ψth(j-top) (K/W):

    21.0

  • Rth(j-c) (K/W):

    68

  • Package name:

    SO14

更新时间:2026-5-20 18:44:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
24+/25+
10
原装正品现货库存价优
恩XP
1810+
NA
2000
恩XP
25+
SOP-14
1539
公司原装现货,热卖中!
恩XP
25+
SOP-14
1539
公司原装现货,热卖中!
PHI
21+
SSOP14
16800
全新原装鄙视假货
ti
25+
500000
行业低价,代理渠道
恩XP
23+
N/A
12000
一级代理,专注军工、汽车、医疗、工业、新能源、电力
恩XP
2025+
SOP
5000
原装进口价格优 请找坤融电子!
Rochester Electronics, LLC
24+25+
16500
全新原厂原装现货!受权代理!可送样可提供技术支持!
24+
5000
公司存货

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