OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

FEATURES · Operate From 1.65 V to 3.6 V · Inputs Accept Voltages to 5.5 V · Max tpd of 7.4 ns at 3.3 V · Typical V OLP (Output Ground Bounce) 2 V at VCC = 3.3 V, TA = 25°C · Support Mixed-Mode Signal Operation on All

OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

FEATURES · Operate From 1.65 V to 3.6 V · Inputs Accept Voltages to 5.5 V · Max tpd of 7.4 ns at 3.3 V · Typical V OLP (Output Ground Bounce) 2 V at VCC = 3.3 V, TA = 25°C · Support Mixed-Mode Signal Operation on All

封装/外壳：24-SOIC（0.209"，5.30mm 宽） 包装：卷带（TR） 描述：IC TXRX NON-INVERT 3.6V 24SO 集成电路（IC） 缓冲器，驱动器，接收器，收发器

OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS

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封装/外壳：24-SOIC（0.209"，5.30mm 宽） 包装：卷带（TR） 描述：IC TXRX NON-INVERT 3.6V 24SO 集成电路（IC） 缓冲器，驱动器，接收器，收发器

Octal bus transceiver/register 3-State

DESCRIPTION The 74LVC646A is a high performance, low-power, low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply voltage range of 1.2V to 3.6V • Flow-through pin-out architecture • In accordance with JEDEC standard no. 8-1A • CM

Octal bus transceiver/register 3-State

DESCRIPTION The 74LVC646A is a high performance, low-power, low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply voltage range of 1.2V to 3.6V • Flow-through pin-out architecture • In accordance with JEDEC standard no. 8-1A • CM

Octal bus transceiver/register 3-State

DESCRIPTION The 74LVC646A is a high performance, low-power, low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply voltage range of 1.2V to 3.6V • Flow-through pin-out architecture • In accordance with JEDEC standard no. 8-1A • CM

Octal bus transceiver/register 3-State

DESCRIPTION The 74LVC646A is a high performance, low-power, low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply voltage range of 1.2V to 3.6V • Flow-through pin-out architecture • In accordance with JEDEC standard no. 8-1A • CM