SN74LVC1G32-Q1 Single 2-input positive-OR gate

1 Features 1• Available in the small 1.45 mm2 Package (DRY) with 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5-V • Supports Down Translation to VCC • Max tpd of 3.6 ns at 3.3-V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3-V • Ioff Support

SN74LVC1G32-Q1 Single 2-input positive-OR gate

文件：1.02362 Mbytes Page：23 Pages

SN74LVC1G32-Q1 Single 2-input positive-OR gate

1 Features 1• Available in the small 1.45 mm2 Package (DRY) with 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5-V • Supports Down Translation to VCC • Max tpd of 3.6 ns at 3.3-V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3-V • Ioff Support

SN74LVC1G32-Q1 Single 2-input positive-OR gate

1 Features 1• Available in the small 1.45 mm2 Package (DRY) with 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5-V • Supports Down Translation to VCC • Max tpd of 3.6 ns at 3.3-V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3-V • Ioff Support

封装/外壳：6-UFDFN 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC GATE OR 1CH 2-INP 6USON 集成电路（IC） 门和反相器

SN74LVC1G32-Q1 Single 2-input positive-OR gate

文件：1.02362 Mbytes Page：23 Pages

Single 2-input OR gate

DESCRIPTION The 74LVC1G32 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply voltage range from 1.65 V to 5.5 V • High noise immunity • Complies with JEDEC standard: – JESD8-7 (1.65 V to 1.95

Single 2-input OR gate

SINGLE 2 INPUT POSITIVE OR GATE

Description The 74LVC1G32 is a single 2-input positive OR gate with a standard push-pull output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to 5.5V allowing this device to be used in a mixed voltage environment. The device is fully spe

Single 2-input OR gate

1. General description The 74LVC1G32 is a single 2-input OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower inp

SINGLE 2-INPUT POSITIVE-OR GATE

文件：444.71 Kbytes Page：17 Pages