SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125-Q1 Single-BUS buffer gate with 3-state output

1 Features • AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature Range – Device Human-Body Model (HBM) ESD Classification Level 2 – Device Charged-Device Model (CDM) ESD Classification Level C5 • Available in the small

SN74LVC1G125-Q1 Single-BUS buffer gate with 3-state output

1 Features • AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature Range – Device Human-Body Model (HBM) ESD Classification Level 2 – Device Charged-Device Model (CDM) ESD Classification Level C5 • Available in the small

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

具有三态输出的增强型产品单路 1.65V 至 5.5V 缓冲器

This bus buffer gate is designed for 1.65-V to 5.5-V VCC operation.The SN74LVC1G125 is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high.This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disabl • Controlled Baseline \n• Enhanced Diminishing Manufacturing Sources (DMS) Support\n• Qualification Pedigree\n• Supports 5-V VCC Operation\n• Max tpd of 3.7 ns at 3.3 V\n• ±24-mA Output Drive at 3.3 V\n• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II\n• 2000-V Human-Body Model (A114-A)\n•;

SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT

文件：373.24 Kbytes Page：13 Pages

SN74LVC1G125-Q1 Single-BUS buffer gate with 3-state output

文件：1.01981 Mbytes Page：23 Pages

Single Bus Buffer Gate With 3-State Output

文件：2.77278 Mbytes Page：43 Pages

SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：119.99 Kbytes Page：8 Pages

SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：119.99 Kbytes Page：8 Pages

SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：119.99 Kbytes Page：8 Pages

Bus buffer/line driver; 3-state

DESCRIPTION The 74LVC1G125 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. FEAT

SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：119.99 Kbytes Page：8 Pages