This users guide describes the characteristics, operation, and use of the TLV320AIC3204EVM-K.

Features • Full-featured evaluation board for the TLV320AIC3204 stereo audio codec. • USB connection to PC provides power, control, and streaming audio data for easy evaluation. • Onboard microphone for ADC evaluation • Connection points for external control and digital audio signals for quick

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125-Q1 Single-BUS buffer gate with 3-state output

1 Features • AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature Range – Device Human-Body Model (HBM) ESD Classification Level 2 – Device Charged-Device Model (CDM) ESD Classification Level C5 • Available in the small

SN74LVC1G125-Q1 Single-BUS buffer gate with 3-state output

1 Features • AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature Range – Device Human-Body Model (HBM) ESD Classification Level 2 – Device Charged-Device Model (CDM) ESD Classification Level C5 • Available in the small

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

Designed for 1.65V to 5.5V VCC Operation

General Description The SN74LVC1G125 is a high performance non−inverting buffer operating from a 1.65V to 5.5V supply. This device is fabricated with advanced CMOS technology to achieve ultra-high speed with high output drive. Features ● Designed for 1.65V to 5.5V VCC Operation ● Overvol

具有三态输出的 1.65V 至 5.5V 单路缓冲器

This bus buffer gate is designed for 1.65-V to 5.5-V VCC operation.The SN74LVC1G125 device is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high.The CMOS device has high output drive while maintaining low static power dissipation over a broad • Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch\n• Inputs Accept Voltages to 5.5 V\n• Max tpd of 3.7 ns at 3.3 V\n• ±24-mA Output Drive at 3.3 V\n• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II\n• 2000-V Human-Body Model (A114-A)\n• 1000-V Charged-Device Model (C;

Single Bus Buffer Gate With 3-State Output

文件：2.77278 Mbytes Page：43 Pages

SN74LVC1G125-Q1 Single-BUS buffer gate with 3-state output

文件：1.01981 Mbytes Page：23 Pages

SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：119.99 Kbytes Page：8 Pages

SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT

文件：738.37 Kbytes Page：19 Pages

SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT

文件：738.1 Kbytes Page：19 Pages

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

丝印代码：C225；Designed for 1.65V to 5.5V VCC Operation

General Description The SN74LVC1G125 is a high performance non−inverting buffer operating from a 1.65V to 5.5V supply. This device is fabricated with advanced CMOS technology to achieve ultra-high speed with high output drive. Features ● Designed for 1.65V to 5.5V VCC Operation ● Overvol

丝印代码：C255；SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

丝印代码：C255；SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

丝印代码：CMF；SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

丝印代码：CM5；SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

丝印代码：CM5；Designed for 1.65V to 5.5V VCC Operation

General Description The SN74LVC1G125 is a high performance non−inverting buffer operating from a 1.65V to 5.5V supply. This device is fabricated with advanced CMOS technology to achieve ultra-high speed with high output drive. Features ● Designed for 1.65V to 5.5V VCC Operation ● Overvol

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

丝印代码：CM5；SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

丝印代码：CM7；SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

丝印代码：DM；Designed for 1.65V to 5.5V VCC Operation

General Description The SN74LVC1G125 is a high performance non−inverting buffer operating from a 1.65V to 5.5V supply. This device is fabricated with advanced CMOS technology to achieve ultra-high speed with high output drive. Features ● Designed for 1.65V to 5.5V VCC Operation ● Overvol

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

SN74LVC1G125-Q1 Single-BUS buffer gate with 3-state output

1 Features • AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature Range – Device Human-Body Model (HBM) ESD Classification Level 2 – Device Charged-Device Model (CDM) ESD Classification Level C5 • Available in the small

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S