SN74LVC126A Quadruple Bus Buffer Gate With 3-State Outputs

1 Features • Operates from 1.65V to 3.6V • Specified from –40°C to +125°C • Inputs accept voltages up to 5.5V • Maximum tpd of 4.7ns at 3.3V • Typical VOLP (output ground bounce), 2V at VCC = 3.3V, TA = 25°C • Latch-u

QUADRPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：508.45 Kbytes Page：16 Pages

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：361.82 Kbytes Page：14 Pages

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC BUF NON-INVERT 3.6V 14SOIC 集成电路（IC） 缓冲器，驱动器，接收器，收发器

SN74LVC126A Quadruple Bus Buffer Gate With 3-State Outputs

1 Features • Operates from 1.65V to 3.6V • Specified from –40°C to +125°C • Inputs accept voltages up to 5.5V • Maximum tpd of 4.7ns at 3.3V • Typical VOLP (output ground bounce), 2V at VCC = 3.3V, TA = 25°C • Latch-u

SN74LVC126A Quadruple Bus Buffer Gate With 3-State Outputs

1 Features • Operates from 1.65V to 3.6V • Specified from –40°C to +125°C • Inputs accept voltages up to 5.5V • Maximum tpd of 4.7ns at 3.3V • Typical VOLP (output ground bounce), 2V at VCC = 3.3V, TA = 25°C • Latch-u

SN74LVC126A Quadruple Bus Buffer Gate With 3-State Outputs

1 Features • Operates from 1.65V to 3.6V • Specified from –40°C to +125°C • Inputs accept voltages up to 5.5V • Maximum tpd of 4.7ns at 3.3V • Typical VOLP (output ground bounce), 2V at VCC = 3.3V, TA = 25°C • Latch-u

SN74LVC126A Quadruple Bus Buffer Gate With 3-State Outputs

1 Features • Operates from 1.65V to 3.6V • Specified from –40°C to +125°C • Inputs accept voltages up to 5.5V • Maximum tpd of 4.7ns at 3.3V • Typical VOLP (output ground bounce), 2V at VCC = 3.3V, TA = 25°C • Latch-u

SN74LVC126A Quadruple Bus Buffer Gate With 3-State Outputs

1 Features • Operates from 1.65V to 3.6V • Specified from –40°C to +125°C • Inputs accept voltages up to 5.5V • Maximum tpd of 4.7ns at 3.3V • Typical VOLP (output ground bounce), 2V at VCC = 3.3V, TA = 25°C • Latch-u

SN74LVC126A Quadruple Bus Buffer Gate With 3-State Outputs

1 Features • Operates from 1.65V to 3.6V • Specified from –40°C to +125°C • Inputs accept voltages up to 5.5V • Maximum tpd of 4.7ns at 3.3V • Typical VOLP (output ground bounce), 2V at VCC = 3.3V, TA = 25°C • Latch-u

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：361.82 Kbytes Page：14 Pages

QUADRPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：508.45 Kbytes Page：16 Pages

QUADRPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：508.45 Kbytes Page：16 Pages

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：361.82 Kbytes Page：14 Pages

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：361.82 Kbytes Page：14 Pages

QUADRPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：508.45 Kbytes Page：16 Pages

QUADRPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：508.45 Kbytes Page：16 Pages

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：361.82 Kbytes Page：14 Pages

QUADRPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：508.45 Kbytes Page：16 Pages

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC BUF NON-INVERT 3.6V 14SOIC 集成电路（IC） 缓冲器，驱动器，接收器，收发器

QUADRPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：508.45 Kbytes Page：16 Pages

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：361.82 Kbytes Page：14 Pages

QUADRPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：508.45 Kbytes Page：16 Pages

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：361.82 Kbytes Page：14 Pages

QUADRPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：508.45 Kbytes Page：16 Pages

QUADRPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：508.45 Kbytes Page：16 Pages

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：361.82 Kbytes Page：14 Pages

QUADRPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：508.45 Kbytes Page：16 Pages

QUADRPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：508.45 Kbytes Page：16 Pages

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：361.82 Kbytes Page：14 Pages

QUADRPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：508.45 Kbytes Page：16 Pages

QUADRPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：508.45 Kbytes Page：16 Pages

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：361.82 Kbytes Page：14 Pages

QUADRPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：508.45 Kbytes Page：16 Pages

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：361.82 Kbytes Page：14 Pages

QUADRPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：508.45 Kbytes Page：16 Pages

Low-Voltage CMOS Quad 2-Input NAND Gate

Low-Voltage CMOS Quad Buffer With 5 V−Tolerant Inputs and Outputs (3−State, Non−Inverting) The 74LVC126A is a high performance, non−inverting quad buffer operating from a 1.2 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL comp

QUADRUPLE 3-STATE BUFFERS

Description The 74LVC126A provides four independent buffers with three state outputs. Each output is independently controlled by an associated output enable pin (OE) which places the device in the high impedance state when driven low. The device is designed for operation with a power supply range

Quad buffer/line driver with 5 V tolerant input/outputs; 3-state

1. General description The 74LVC126A is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A LOW on nOE causes the outputs to assume a high impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these

Quad buffer/line driver with 5 Volt tolerant input/outputs; 3-state

DESCRIPTION The 74LVC126A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 V. The 74LVC126A consists of four non-inver

Quad buffer/line driver with 5 Volt tolerant input/outputs; 3-state

DESCRIPTION The 74LVC126A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 V. The 74LVC126A consists of four non-inver