Low-Voltage CMOS Quad 2-Input NAND Gate

Low-Voltage CMOS Quad Buffer With 5 V−Tolerant Inputs and Outputs (3−State, Non−Inverting) The 74LVC126A is a high performance, non−inverting quad buffer operating from a 1.2 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL comp

Quad buffer/line driver with 5 Volt tolerant input/outputs; 3-state

DESCRIPTION The 74LVC126A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 V. The 74LVC126A consists of four non-inver

QUADRUPLE 3-STATE BUFFERS

Description The 74LVC126A provides four independent buffers with three state outputs. Each output is independently controlled by an associated output enable pin (OE) which places the device in the high impedance state when driven low. The device is designed for operation with a power supply range

Quad buffer/line driver with 5 V tolerant input/outputs; 3-state

1. General description The 74LVC126A is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A LOW on nOE causes the outputs to assume a high impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these

Quad Buffer with 3-State Output

The 74LVC126A that provides a quad buffer with 3-state output is designed for 1.65V to 3.6V VCC operation. Both 3.3V and 5V devices can drive inputs, enabling this device to operate as a translator in a mixed 3.3V and 5V system environment. The 3-state outputs are controlled by the output enable inp ● Wide Supply Voltage Range: 1.65V to 3.6V \n● Inputs Accept Voltages up to 5.5V\n● Propagation Delay: 3.3ns (TYP) at VCC = 3.3V\n● Output Ground Bounce VOLP (TYP) < 0.8V at VCC = 3.3V and TA = +25℃\n● Output VOH Undershoot VOHV (TYP) > 2V at VCC = 3.3V and TA = +25℃\n● 3-State Output\n● Separate OE;

Standard-logic

The 74LVC126A provides four independent buffers with three\nstate outputs. Each output is independently control°C by an\nassociated output enable pin (OE) which places the device in\nthe high impedance state when driven low. The device is\ndesigned for operation with a power supply range of 1.65V to

LOW VOLTAGE CMOS QUAD BUS BUFFERS (3-STATE) HIGH PERFORMANCE

Quad buffer/line driver with 5 V tolerant input/outputs; 3-state

1. General description The 74LVC126A is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A LOW on nOE causes the outputs to assume a high impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these

Quad buffer/line driver with 5 Volt tolerant input/outputs; 3-state

DESCRIPTION The 74LVC126A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 V. The 74LVC126A consists of four non-inver

Quad buffer/line driver with 5 V tolerant input/outputs; 3-state

General description The 74LVC126A-Q100 consists of four non-inverting buffers/line drivers with 3-state outputs, which are controlled by the output enable input (nOE). A LOW at nOE causes the outputs to assume a high-impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. Whe

Quad buffer/line driver with 5 V tolerant input/outputs; 3-state

1. General description The 74LVC126A is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A LOW on nOE causes the outputs to assume a high impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these

Quad buffer/line driver with 5 Volt tolerant input/outputs; 3-state

DESCRIPTION The 74LVC126A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 V. The 74LVC126A consists of four non-inver

Quad buffer/line driver with 5 Volt tolerant input/outputs; 3-state

DESCRIPTION The 74LVC126A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 V. The 74LVC126A consists of four non-inver

Quad buffer/line driver with 5 V tolerant input/outputs; 3-state

General description The 74LVC126A-Q100 consists of four non-inverting buffers/line drivers with 3-state outputs, which are controlled by the output enable input (nOE). A LOW at nOE causes the outputs to assume a high-impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. Whe

Low-Voltage CMOS Quad 2-Input NAND Gate

Low-Voltage CMOS Quad Buffer With 5 V−Tolerant Inputs and Outputs (3−State, Non−Inverting) The 74LVC126A is a high performance, non−inverting quad buffer operating from a 1.2 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL comp

Low-Voltage CMOS Quad 2-Input NAND Gate

Low-Voltage CMOS Quad Buffer With 5 V−Tolerant Inputs and Outputs (3−State, Non−Inverting) The 74LVC126A is a high performance, non−inverting quad buffer operating from a 1.2 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL comp

Quad buffer/line driver with 5 Volt tolerant input/outputs; 3-state

DESCRIPTION The 74LVC126A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 V. The 74LVC126A consists of four non-inver

Quad buffer/line driver with 5 V tolerant input/outputs; 3-state

1. General description The 74LVC126A is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A LOW on nOE causes the outputs to assume a high impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these

Quad buffer/line driver with 5 V tolerant input/outputs; 3-state

General description The 74LVC126A-Q100 consists of four non-inverting buffers/line drivers with 3-state outputs, which are controlled by the output enable input (nOE). A LOW at nOE causes the outputs to assume a high-impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. Whe

Quad buffer/line driver with 5 V tolerant input/outputs; 3-state

General description The 74LVC126A-Q100 consists of four non-inverting buffers/line drivers with 3-state outputs, which are controlled by the output enable input (nOE). A LOW at nOE causes the outputs to assume a high-impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. Whe

QUADRUPLE 3-STATE BUFFERS

Description The 74LVC126A provides four independent buffers with three state outputs. Each output is independently controlled by an associated output enable pin (OE) which places the device in the high impedance state when driven low. The device is designed for operation with a power supply range

QUADRUPLE 3-STATE BUFFERS

Description The 74LVC126A provides four independent buffers with three state outputs. Each output is independently controlled by an associated output enable pin (OE) which places the device in the high impedance state when driven low. The device is designed for operation with a power supply range

QUADRUPLE 3-STATE BUFFERS

Description The 74LVC126A provides four independent buffers with three state outputs. Each output is independently controlled by an associated output enable pin (OE) which places the device in the high impedance state when driven low. The device is designed for operation with a power supply range

QUADRUPLE 3-STATE BUFFERS

Description The 74LVC126A provides four independent buffers with three state outputs. Each output is independently controlled by an associated output enable pin (OE) which places the device in the high impedance state when driven low. The device is designed for operation with a power supply range

封装/外壳：14-VFQFN 裸露焊盘 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC BUF NON-INVERT 3.6V 14DHVQFN 集成电路（IC） 缓冲器，驱动器，接收器，收发器

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC BUFFER NON-INVERT 3.6V 14SO 集成电路（IC） 缓冲器，驱动器，接收器，收发器

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：361.82 Kbytes Page：14 Pages

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：361.82 Kbytes Page：14 Pages

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：361.82 Kbytes Page：14 Pages

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：361.82 Kbytes Page：14 Pages

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：361.82 Kbytes Page：14 Pages