丝印代码：LV138AT；3-LINE TO 8-LINE DECODER/DEMULTIPLEXER

FEATURES · Inputs Are TTL-Voltage Compatible · 4.5-V to 5.5-V V CC Operation · Max tpd of 7.6 ns at 5 V · Typical V OLP (Output Ground Bounce) 2.3 V at VCC = 5 V, TA = 25°C · Support Mixed-Mode Voltage Operation on All

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC DECODER/DEMUX 1X3:8 16SOIC 集成电路（IC） 信号开关，多路复用器，解码器

3-LINE TO 8-LINE DECODER/DEMULTIPLEXER

文件：984.51 Kbytes Page：19 Pages

3-LINE TO 8-LINE DECODER/DEMULTIPLEXER

文件：867.62 Kbytes Page：20 Pages

丝印代码：LV138AT；3-LINE TO 8-LINE DECODER/DEMULTIPLEXER

FEATURES · Inputs Are TTL-Voltage Compatible · 4.5-V to 5.5-V V CC Operation · Max tpd of 7.6 ns at 5 V · Typical V OLP (Output Ground Bounce) 2.3 V at VCC = 5 V, TA = 25°C · Support Mixed-Mode Voltage Operation on All

3-LINE TO 8-LINE DECODER/DEMULTIPLEXER

文件：867.62 Kbytes Page：20 Pages

3-LINE TO 8-LINE DECODER/DEMULTIPLEXER

文件：867.62 Kbytes Page：20 Pages

3-to-8 line decoder/multiplexer; inverting

DESCRIPTION The 74LV138 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT138. The 74LV138 accepts three binary weighted address inputs (A0, A1, A2) and when enabled, provide 8 mutually exclusive active LOW outputs (Y0 to Y7). FEATURES • Wide operatin

3-to-8 line decoder/multiplexer; inverting

DESCRIPTION The 74LV138 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT138. The 74LV138 accepts three binary weighted address inputs (A0, A1, A2) and when enabled, provide 8 mutually exclusive active LOW outputs (Y0 to Y7). FEATURES • Wide operatin

3-to-8 line decoder/multiplexer; inverting

DESCRIPTION The 74LV138 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT138. The 74LV138 accepts three binary weighted address inputs (A0, A1, A2) and when enabled, provide 8 mutually exclusive active LOW outputs (Y0 to Y7). FEATURES • Wide operatin

3-to-8 line decoder/multiplexer; inverting

DESCRIPTION The 74LV138 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT138. The 74LV138 accepts three binary weighted address inputs (A0, A1, A2) and when enabled, provide 8 mutually exclusive active LOW outputs (Y0 to Y7). FEATURES • Wide operatin

3-to-8 line decoder/multiplexer; inverting

DESCRIPTION The 74LV138 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT138. The 74LV138 accepts three binary weighted address inputs (A0, A1, A2) and when enabled, provide 8 mutually exclusive active LOW outputs (Y0 to Y7). FEATURES • Wide operatin