3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

文件：378.66 Kbytes Page：16 Pages

封装/外壳：16-SOIC（0.209"，5.30mm 宽） 包装：管件 描述：IC DECODER/DEMUX 1 X 3:8 16SO 集成电路（IC） 信号开关，多路复用器，解码器

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

FEATURES · 2-V to 5.5-V VCC Operation · Max t pd of 9.5 ns at 5 V · Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 3.3 V, TA = 25°C · Support Mixed-Mode Voltage Operation on All Ports · Ioff Supports Partial-Pow

封装/外壳：16-SOIC（0.209"，5.30mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC DECODER/DEMUX 1 X 3:8 16SO 集成电路（IC） 信号开关，多路复用器，解码器

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

文件：378.66 Kbytes Page：16 Pages

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

文件：649.05 Kbytes Page：18 Pages

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

文件：749.82 Kbytes Page：22 Pages

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

文件：749.82 Kbytes Page：22 Pages

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

文件：649.05 Kbytes Page：18 Pages

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

文件：378.66 Kbytes Page：16 Pages

3-to-8 line decoder/multiplexer; inverting

DESCRIPTION The 74LV138 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT138. The 74LV138 accepts three binary weighted address inputs (A0, A1, A2) and when enabled, provide 8 mutually exclusive active LOW outputs (Y0 to Y7). FEATURES • Wide operatin

3-to-8 line decoder/demultiplexer; inverting

3-to-8 line decoder/demultiplexer; inverting

1. General description The 74LV138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The 74LVC138A features three enable inputs (Y1, Y2 and E3). Every output will be HIGH unless Y1 and Y2 are LOW and E3 is HIGH. This multiple enable fun

3-to-8 line decoder/demultiplexer; inverting

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

文件：649.05 Kbytes Page：18 Pages