HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

“174, 'LS174, ‘S174 Contain Six Flip-Flops with Single-Rail Outputs ‘175, 'L.S175, ‘S175 Contain Four Flip-Flops with Double-Rail Outputs Three Performance Ranges Offered: See Table Lower Right Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications incl

HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

“174, 'LS174, ‘S174 Contain Six Flip-Flops with Single-Rail Outputs ‘175, 'L.S175, ‘S175 Contain Four Flip-Flops with Double-Rail Outputs Three Performance Ranges Offered: See Table Lower Right Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications incl

封装/外壳：16-SOIC（0.209"，5.30mm 宽） 功能：主复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE SNGL 6BIT 16SO 集成电路（IC） 触发器

HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

文件：403.5 Kbytes Page：13 Pages

HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

文件：668 Kbytes Page：14 Pages

HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

文件：698.53 Kbytes Page：14 Pages

HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

文件：403.5 Kbytes Page：13 Pages

HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

文件：668 Kbytes Page：14 Pages

HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

文件：403.5 Kbytes Page：13 Pages

HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

文件：668 Kbytes Page：14 Pages

Hex/Quad D-Type Flip-Flops with Clear

General Description These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the quad (175) versions feature complementary outputs from each flip-flop. Information at the D inputs meeting the setup time require ments i

LOW POWER SCHOTTKY

The LSTTL/MSI SN74LS174 is a high speed Hex D Flip-Flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW to HIGH clock transition. The device has a Master Reset to simultaneously clear all flip-flops.

Hex/Quadruple D-type Flip-Flips(with clear)

HEX D FLIP-FLOP

The LSTTL/MSI SN54/74LS174 is a high speed Hex D Flip-Flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW to HIGH clock transition. The device has a Master Reset to simultaneously clear all flip-flo

Hex/Quad D Flip-Flops with Clear

文件：174.65 Kbytes Page：8 Pages

Hex/Quad D Flip-Flops with Clear

LOW POWER SCHOTTKY

HEX D FLIP-FLOP

Hex/Quad D-Type Flip-Flops with Clear

Hex/Quadruple D-type Flip-Flips(with clear)

Hex/Quad D Flip-Flops with Clear

Hex/Quad D-Type Flip-Flops with Clear

Ouadruple 2-input Positive NAND Gates

Hex / Quadruple D-type Flip-Flops (with clear)

Hex/Quadruple D-type Flip-Flips(with clear)

Hex / Quadruple D-type Flip-Flops (with clear)

HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

LOW POWER SCHOTTKY

HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

LOW POWER SCHOTTKY

HEX D FLIP-FLOP

HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR