SN74HCT165 8-Bit Parallel-Load Shift Registers

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • 4.5 V to 5.5 V operation • Supports fanout up to 10 LSTTL loads • Direct overriding load (data) inputs • Gated clock inputs • Extended ambient temperature r

SN74HCT165-Q1 Automotive 8-Bit Parallel-Load Shift Registers

1 Features • AEC-Q100 qualified for automotive applications: – Device temperature grade 1: • –40°C to +125°C, TA – Device HBM ESD Classification Level 2 – Device CDM ESD Classification Level C6 • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible

8 位并行输入/串行输出移位寄存器

SN74HCT165 8-Bit Parallel-Load Shift Registers

文件：1.11807 Mbytes Page：27 Pages

SN74HCT165-Q1 Automotive 8-Bit Parallel-Load Shift Registers

文件：1.12002 Mbytes Page：27 Pages

SN74HCT165-Q1 Automotive 8-Bit Parallel-Load Shift Registers

文件：1.38867 Mbytes Page：24 Pages

SN74HCT165 8-Bit Parallel-Load Shift Registers

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • 4.5 V to 5.5 V operation • Supports fanout up to 10 LSTTL loads • Direct overriding load (data) inputs • Gated clock inputs • Extended ambient temperature r

SN74HCT165-Q1 Automotive 8-Bit Parallel-Load Shift Registers

1 Features • AEC-Q100 qualified for automotive applications: – Device temperature grade 1: • –40°C to +125°C, TA – Device HBM ESD Classification Level 2 – Device CDM ESD Classification Level C6 • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible

SN74HCT165 8-Bit Parallel-Load Shift Registers

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • 4.5 V to 5.5 V operation • Supports fanout up to 10 LSTTL loads • Direct overriding load (data) inputs • Gated clock inputs • Extended ambient temperature r

SN74HCT165 8-Bit Parallel-Load Shift Registers

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • 4.5 V to 5.5 V operation • Supports fanout up to 10 LSTTL loads • Direct overriding load (data) inputs • Gated clock inputs • Extended ambient temperature r

SN74HCT165-Q1 Automotive 8-Bit Parallel-Load Shift Registers

1 Features • AEC-Q100 qualified for automotive applications: – Device temperature grade 1: • –40°C to +125°C, TA – Device HBM ESD Classification Level 2 – Device CDM ESD Classification Level C6 • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible

SN74HCT165 8-Bit Parallel-Load Shift Registers

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • 4.5 V to 5.5 V operation • Supports fanout up to 10 LSTTL loads • Direct overriding load (data) inputs • Gated clock inputs • Extended ambient temperature r

SN74HCT165-Q1 Automotive 8-Bit Parallel-Load Shift Registers

1 Features • AEC-Q100 qualified for automotive applications: – Device temperature grade 1: • –40°C to +125°C, TA – Device HBM ESD Classification Level 2 – Device CDM ESD Classification Level C6 • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible

SN74HCT165-Q1 Automotive 8-Bit Parallel-Load Shift Registers

1 Features • AEC-Q100 qualified for automotive applications: – Device temperature grade 1: • –40°C to +125°C, TA – Device HBM ESD Classification Level 2 – Device CDM ESD Classification Level C6 • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible

SN74HCT165 8-Bit Parallel-Load Shift Registers

文件：1.38725 Mbytes Page：24 Pages

SN74HCT165 8-Bit Parallel-Load Shift Registers

文件：1.11807 Mbytes Page：27 Pages

SN74HCT165 8-Bit Parallel-Load Shift Registers

文件：1.38725 Mbytes Page：24 Pages

SN74HCT165-Q1 Automotive 8-Bit Parallel-Load Shift Registers

文件：1.12002 Mbytes Page：27 Pages

SN74HCT165-Q1 Automotive 8-Bit Parallel-Load Shift Registers

文件：1.38867 Mbytes Page：24 Pages

SN74HCT165 8-Bit Parallel-Load Shift Registers

文件：1.38725 Mbytes Page：24 Pages

封装/外壳：16-TSSOP（0.173"，4.40mm 宽） 功能：并行至串行 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：8-BIT PARALLEL-IN/SERIAL-OUT SHI 集成电路（IC） 移位寄存器

具有 TLL 兼容输入的汽车类 8 位并行负载移位寄存器

SN74HCT165-Q1 Automotive 8-Bit Parallel-Load Shift Registers

文件：1.12002 Mbytes Page：27 Pages

SN74HCT165 8-Bit Parallel-Load Shift Registers

文件：1.11807 Mbytes Page：27 Pages

SN74HCT165 8-Bit Parallel-Load Shift Registers

文件：1.38725 Mbytes Page：24 Pages

SN74HCT165-Q1 Automotive 8-Bit Parallel-Load Shift Registers

文件：1.38867 Mbytes Page：24 Pages

SN74HCT165-Q1 Automotive 8-Bit Parallel-Load Shift Registers

文件：1.38867 Mbytes Page：24 Pages

SN74HCT165-Q1 Automotive 8-Bit Parallel-Load Shift Registers

文件：1.38867 Mbytes Page：24 Pages

封装/外壳：16-TSSOP（0.173"，4.40mm 宽） 功能：并行至串行 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：AUTOMOTIVE 8-BIT PARALLEL LOAD S 集成电路（IC） 移位寄存器

8-bit parallel-in/serial out shift register

1. General description The 74HC165; 74HCT165 are 8-bit serial or parallel-in/serial-out shift registers. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 and Q7). When the parallel load input (PL) is LOW the data from D

8-bit parallel-in/serial-out shift register

GENERAL DESCRIPTION The 74HC/HCT165 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous 8-bit parallel load • Synchronous serial input • Output capability: standard

8-bit parallel-in/serial out shift register

8-bit parallel-in/serial out shift register

8-bit parallel-in/serial out shift register

1. General description The 74HC165; 74HCT165 are 8-bit serial or parallel-in/serial-out shift registers. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 and Q7). When the parallel load input (PL) is LOW the data from D