SN74HCT165 8-Bit Parallel-Load Shift Registers

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • 4.5 V to 5.5 V operation • Supports fanout up to 10 LSTTL loads • Direct overriding load (data) inputs • Gated clock inputs • Extended ambient temperature r

8-bit parallel-in/serial out shift register

1. General description The 74HC165; 74HCT165 are 8-bit serial or parallel-in/serial-out shift registers. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 and Q7). When the parallel load input (PL) is LOW the data from D

8-bit parallel-in/serial-out shift register

GENERAL DESCRIPTION The 74HC/HCT165 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous 8-bit parallel load • Synchronous serial input • Output capability: standard

8-bit parallel-in/serial out shift register

8-bit parallel-in/serial out shift register

8-bit parallel-in/serial out shift register

1. General description The 74HC165; 74HCT165 are 8-bit serial or parallel-in/serial-out shift registers. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 and Q7). When the parallel load input (PL) is LOW the data from D