3-LINE TO 8-LINE DECODERS DEMULTIPLEXERS

文件：1.13482 Mbytes Page：21 Pages

3-LINE TO 8-LINE DECODER/DEMULTIPLEXER

文件：1.10892 Mbytes Page：20 Pages

3-to-8 line decoder/demultiplexer inverting

3-to-8 line decoder/demultiplexer; inverting

1. General description The 74HC138; 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple ena

3-to-8 line decoder/demultiplexer; inverting

GENERAL DESCRIPTION The 74HC/HCT138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Demultiplexing capability • Multiple input enable for easy expansion • Ideal for memory

3 TO 8 LINE DECODER DEMULTIPLEXER

文件：246.31 Kbytes Page：10 Pages

3-to-8 line decoder/demultiplexer; inverting