4-BIT SYNCHRONOUS UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)

Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-μA Max ICC Typical tpd = 20 ns ±4-mA Output Drive at 5 V Low Input Current of 1 μA Max Look-Ahead Circuitry Enhances Cascaded Counters Fully Synchronous in Count Modes Parallel Asyn

4-BIT SYNCHRONOUS UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)

Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-μA Max ICC Typical tpd = 20 ns ±4-mA Output Drive at 5 V Low Input Current of 1 μA Max Look-Ahead Circuitry Enhances Cascaded Counters Fully Synchronous in Count Modes Parallel Asyn

封装/外壳：16-SOIC（0.209"，5.30mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC BINARY COUNTER UP/DOWN 16SO 集成电路（IC） 计数器，除法器

4-BIT SYNCHRONOUS UP/DOWN COUNTERS DUAL CLOCK WITH CLEAR

文件：483.09 Kbytes Page：17 Pages

4-BIT SYNCHRONOUS UP/DOWN COUNTERS DUAL CLOCK WITH CLEAR

文件：1.07063 Mbytes Page：21 Pages

4-BIT SYNCHRONOUS UP/DOWN COUNTERS DUAL CLOCK WITH CLEAR

文件：483.09 Kbytes Page：17 Pages

Presettable synchronous 4-bit binary up/down counter

Presettable synchronous 4-bit binary up/down counter

1. General description The 74HC193; 74HCT193 is a 4-bit synchronous binary up/down counter. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed while CPD i

Presettable synchronous 4-bit binary up/down counter

GENERAL DESCRIPTION The 74HC/HCT193 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Synchronous reversible 4-bit binary counting • Asynchronous parallel load • Asynchronous

Presettable synchronous 4-bit binary up/down counter

GENERAL DESCRIPTION The 74HC/HCT193 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Synchronous reversible 4-bit binary counting • Asynchronous parallel load • Asynchronous

Presettable synchronous 4-bit binary up/down counter