Presettable synchronous 4-bit binary up/down counter

GENERAL DESCRIPTION The 74HC/HCT193 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Synchronous reversible 4-bit binary counting • Asynchronous parallel load • Asynchronous

Presettable synchronous 4-bit binary up/down counter

Presettable synchronous 4-bit binary up/down counter

1. General description The 74HC193; 74HCT193 is a 4-bit synchronous binary up/down counter. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed while CPD i

Presettable synchronous 4-bit binary up/down counter

The 74HC193; 74HCT193 is a 4-bit synchronous binary up/down counter. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed while CPD is held HIGH, the device will • Input levels:• For 74HC193: CMOS level\n• For 74HCT193: TTL level\n\n• Synchronous reversible 4-bit binary counting\n• Asynchronous parallel load\n• Asynchronous reset\n• Expandable without external logic\n• Complies with JEDEC standard no. 7A\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n•;

Presettable synchronous 4-bit binary up/down counter

Presettable synchronous 4-bit binary up/down counter

74HC193DB-Q100 - Presettable synchronous 4-bit binary up/down counter

Presettable synchronous 4-bit binary up/down counter - The 74HC193-Q100; 74HCT193-Q100 is a 4-bit synchronous binary up/down counter. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either clock input. I ·Automotive product qualification in accordance with AEC-Q100 (Grade 1)·Specified from -40 °C to +85 °C and from -40 °C to +125 °C;

Presettable synchronous 4-bit binary up/down counter

1. General description The 74HC193-Q100; 74HCT193-Q100 is a 4-bit synchronous binary up/down counter. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed

Presettable synchronous 4-bit binary up/down counter

The 74HC193-Q100; 74HCT193-Q100 is a 4-bit synchronous binary up/down counter. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed while CPD is held HIGH, the d • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Input levels:• For 74HC193-Q100: CMOS level\n• For 74HCT193-Q100: TTL level\n\n• Synchronous reversible 4-bit binary counting\n• Asynchronous parallel load\n• Asy;

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC 4BIT BINAR UP/DN COUNT 16SOIC 集成电路（IC） 计数器，除法器

Presettable synchronous 4-bit binary up/down counter

封装/外壳：16-SSOP（0.209"，5.30mm 宽） 包装：管件 描述：IC SYNC 4BIT BINARY UP/DN 16SSOP 集成电路（IC） 计数器，除法器

Presettable synchronous 4-bit binary up/down counter

文件：776.98 Kbytes Page：29 Pages

Presettable synchronous 4-bit binary up/down counter

文件：776.98 Kbytes Page：29 Pages

Presettable synchronous 4-bit binary up/down counter

GENERAL DESCRIPTION The 74HC/HCT193 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Synchronous reversible 4-bit binary counting • Asynchronous parallel load • Asynchronous

Presettable synchronous 4-bit binary up/down counter

GENERAL DESCRIPTION The 74HC/HCT193 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Synchronous reversible 4-bit binary counting • Asynchronous parallel load • Asynchronous

High Speed CMOS Logic Presettable Synchronous 4-Bit Up/Down Counters

文件：67.13 Kbytes Page：11 Pages

4-BIT SYNCHRONOUS UP/DOWN COUNTERS DUAL CLOCK WITH CLEAR

文件：483.09 Kbytes Page：17 Pages