QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

4.5-V to 5.5-V VCC Operation Max tpd of 6.5 ns at 5 V 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers description/ordering information The SN74F126 bus buffer features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enab

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：586.88 Kbytes Page：12 Pages

封装/外壳：14-SOIC（0.209"，5.30mm 宽） 包装：卷带（TR） 描述：IC BUFFER NON-INVERT 5.5V 14SOP 集成电路（IC） 缓冲器，驱动器，接收器，收发器

封装/外壳：14-SOIC（0.209"，5.30mm 宽） 包装：卷带（TR） 描述：IC BUFFER NON-INVERT 5.5V 14SOP 集成电路（IC） 缓冲器，驱动器，接收器，收发器

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：66.22 Kbytes Page：5 Pages

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：66.22 Kbytes Page：5 Pages

Quad buffers 3-State

FEATURE • High impedance NPN base inputs for reduced loading (20µA in High and Low states)

Quad buffers 3-State

FEATURE • High impedance NPN base inputs for reduced loading (20µA in High and Low states)

Quad buffers 3-State

FEATURE • High impedance NPN base inputs for reduced loading (20µA in High and Low states)