QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

4.5-V to 5.5-V VCC Operation Max tpd of 6.5 ns at 5 V 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers description/ordering information The SN74F126 bus buffer features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enab

具有三态输出的 4 通道、4.5V 至 5.5V 双极缓冲器

The SN74F126 bus buffer features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.\n\n To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value o • 4.5-V to 5.5-V VC Operation\n• Max tpd of 6.5 ns at 5 V\n• 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers;

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：586.88 Kbytes Page：12 Pages

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

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丝印代码：SN74F126N；QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

4.5-V to 5.5-V VCC Operation Max tpd of 6.5 ns at 5 V 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers description/ordering information The SN74F126 bus buffer features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enab

丝印代码：SN74F126N；QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

4.5-V to 5.5-V VCC Operation Max tpd of 6.5 ns at 5 V 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers description/ordering information The SN74F126 bus buffer features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enab

丝印代码：F126；QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

4.5-V to 5.5-V VCC Operation Max tpd of 6.5 ns at 5 V 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers description/ordering information The SN74F126 bus buffer features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enab

丝印代码：F126；QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

4.5-V to 5.5-V VCC Operation Max tpd of 6.5 ns at 5 V 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers description/ordering information The SN74F126 bus buffer features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enab

丝印代码：F126；QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

4.5-V to 5.5-V VCC Operation Max tpd of 6.5 ns at 5 V 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers description/ordering information The SN74F126 bus buffer features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enab

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

4.5-V to 5.5-V VCC Operation Max tpd of 6.5 ns at 5 V 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers description/ordering information The SN74F126 bus buffer features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enab

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：586.88 Kbytes Page：12 Pages

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：66.22 Kbytes Page：5 Pages

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：586.88 Kbytes Page：12 Pages

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：586.88 Kbytes Page：12 Pages

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：586.88 Kbytes Page：12 Pages

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC BUF NON-INVERT 5.5V 14SOIC 集成电路（IC） 缓冲器，驱动器，接收器，收发器

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：586.88 Kbytes Page：12 Pages

封装/外壳：14-DIP（0.300"，7.62mm） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC BUF NON-INVERT 5.5V 14DIP 集成电路（IC） 缓冲器，驱动器，接收器，收发器

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：586.88 Kbytes Page：12 Pages

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：66.22 Kbytes Page：5 Pages

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：586.88 Kbytes Page：12 Pages

Quad buffers 3-State

FEATURE • High impedance NPN base inputs for reduced loading (20µA in High and Low states)

Quad buffers 3-State

FEATURE • High impedance NPN base inputs for reduced loading (20µA in High and Low states)

Quad buffers 3-State

FEATURE • High impedance NPN base inputs for reduced loading (20µA in High and Low states)