DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

Inputs Are TTL-Voltage Compatible Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body

Dual 2-to-4 line decoder/demultiplexer

1. General description The 74AHC139; 74AHCT139 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC139; 74AHCT139 is a high-speed, dual 2-to-4 line decoder/demultiplexer. This device

Dual 2-to-4 line decoder/demultiplexer

DESCRIPTION The 74AHC/AHCT139 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74AHC/AHCT139 are high-speed, dual 2-to-4 line decoder/demultiplexers. This device has two independent d

Dual 2-to-4 line decoder/demultiplexer

DESCRIPTION The 74AHC/AHCT139 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74AHC/AHCT139 are high-speed, dual 2-to-4 line decoder/demultiplexers. This device has two independent d

Dual 2-to-4 line decoder/demultiplexer

1. General description The 74AHC139; 74AHCT139 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC139; 74AHCT139 is a high-speed, dual 2-to-4 line decoder/demultiplexer. This device

Dual 2-to-4 line decoder/demultiplexer