SNx4AHC74 Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset

1 Features • Operating range 2-V to 5.5-V VCC • Latch-up performance exceeds 250 mA per JESD 17 • ESD protection exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) 2 Applications • Convert a momentary switch to a toggle

SNx4AHC74 Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset

1 Features • Operating range 2V to 5.5V VCC • Latch-up performance exceeds 250mA per JESD 17 • ESD protection exceeds JESD 22 – 2000V Human-Body Model (A114-A) – 200V Machine Model (A115-A) – 1000V Charged-Device Model (C101) 2 Applications • Convert a momentary switch to a toggle switc

SNx4AHC74 Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset

1 Features • Operating range 2V to 5.5V VCC • Latch-up performance exceeds 250mA per JESD 17 • ESD protection exceeds JESD 22 – 2000V Human-Body Model (A114-A) – 200V Machine Model (A115-A) – 1000V Charged-Device Model (C101) 2 Applications • Convert a momentary switch to a toggle switc

封装/外壳：14-SOIC（0.209"，5.30mm 宽） 功能：设置（预设）和复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE DUAL 1BIT 14SOP 集成电路（IC） 触发器

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

文件：105.64 Kbytes Page：19 Pages

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

文件：891.27 Kbytes Page：21 Pages

Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset

文件：1.79753 Mbytes Page：27 Pages

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

文件：105.64 Kbytes Page：19 Pages

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

文件：891.27 Kbytes Page：21 Pages

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74AHC/AHCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V

Dual D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC74; 74AHCT74 is a dual positive-edge triggered, D-type flip-flop with individual data

Dual D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC74; 74AHCT74 is a dual positive-edge triggered, D-type flip-flop with individual data

Dual D-type flip-flop with set and reset; positive-edge trigger

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74AHC/AHCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V