SN74AHC595 8-Bit Shift Registers With 3-State Output Registers

1 Features 1• Operating Range: 2-V to 5.5-V VCC • 8-Bit Serial-In, Parallel-Out Shift • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) 2 Appl

SN74AHC595 8-Bit Shift Registers With 3-State Output Registers

1 Features • Operating range: 2V to 5.5V VCC • 8-bit serial-in, parallel-out shift • Latch-up performance exceeds 100mA per JESD 78, class II • ESD protection exceeds JESD 22 – 2000V human-body model (A114-A) – 1000V charged-device model (C101) 2 Applications • Network Switches • Power

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：串行至并行，串行 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC SHIFT REGISTER 8BIT 16-SOIC 集成电路（IC） 移位寄存器

8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS

文件：163.94 Kbytes Page：17 Pages

8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS

文件：729.33 Kbytes Page：20 Pages

8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS

文件：588.83 Kbytes Page：19 Pages

8-Bit Shift Registers

文件：1.021 Mbytes Page：29 Pages

8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS

文件：163.94 Kbytes Page：17 Pages

8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS

文件：588.83 Kbytes Page：19 Pages

8-Bit Shift Registers

文件：1.021 Mbytes Page：29 Pages

8-Bit Shift Registers

文件：1.021 Mbytes Page：29 Pages

8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS

文件：588.83 Kbytes Page：19 Pages

8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

DESCRIPTION The 74AHC/AHCT595 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT595 is an 8-stage serial shift register with a storage register and 3-state outputs. The s

8-BIT SHIFT REGISTER WITH 8-BIT OUTPUT REGISTER

Description The 74AHC595 is an advanced high speed CMOS device. An eight bit shift register accepts data from the serial input (DS) on each positive transition of the shift register clock (STCP). When asserted low the reset function (MR) sets all shift register values to zero and is independ

8-bit serial-in/serial-out or parallel-out shift register with output latches

1. General description The 74AHC595; 74AHCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading

8-bit serial-in/serial-out or parallel-out shift register with output latches

1. General description The 74AHC595; 74AHCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading

NPN general-purpose double transistors output latches; 3-state