8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

DESCRIPTION The 74AHC/AHCT595 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT595 is an 8-stage serial shift register with a storage register and 3-state outputs. The s

8-BIT SHIFT REGISTER WITH 8-BIT OUTPUT REGISTER

Description The 74AHC595 is an advanced high speed CMOS device. An eight bit shift register accepts data from the serial input (DS) on each positive transition of the shift register clock (STCP). When asserted low the reset function (MR) sets all shift register values to zero and is independ

Advanced High Speed CMOS Logic

Features:  High Frequency: 110 MHz (Min) VCC = 5V, CL = 15pF  Output Drive Capability: 15 LSTTL Loads  Low Input Current: 0.1μA  Outputs directly interface CMOS, NMOS and TTL  CMOS High Noise Immunity  Function compatible with 74LS595  Performance upgrade for 74AC595, 74HC595  Exte

8-bit serial-in/serial-out or parallel-out shift register with output latches

1. General description The 74AHC595; 74AHCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading

standard-logic

The 74AHC595 is an advanced high speed CMOS device. \nAn eight bit shift register accpets data from the serial input (DS) on each positive transition of the shift register clock (STCP). When asserted low the reset function /MR sets all shift register values to zero and is indepent of all clocks.\

8-bit serial-in/serial-out or parallel-out shift register with output latches

1. General description The 74AHC595; 74AHCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading

8-bit serial-in/serial-out or parallel-out shift register with output latches

The 74AHC595-Q100; 74AHCT595-Q100 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A.\n The 74AHC595-Q100; 74AHCT595-Q100 are 8-stage serial shift registers with a storage register and 3-state • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Balanced propagation delays\n• All inputs have Schmitt trigger action\n• Inputs accept voltages higher than VCC\n• Input levels:• The 74AHC595-Q100 operates with ;

8-bit serial-in/serial-out or parallel-out shift register

The 74AHC595; 74AHCT595 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A.\n The 74AHC595; 74AHCT595 are 8-stage serial shift registers with a storage register and 3-state outputs. The regist • Balanced propagation delays\n• All inputs have Schmitt-trigger action\n• Inputs accept voltages higher than VCC\n• Input levels:• The 74AHC595 operates with CMOS input levels\n• The 74AHCT595 operates with TTL input levels\n\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A e;

8-bit serial-in/serial-out or parallel-out shift register with output latches

1. General description The 74AHC595; 74AHCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading

8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

DESCRIPTION The 74AHC/AHCT595 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT595 is an 8-stage serial shift register with a storage register and 3-state outputs. The s

8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

DESCRIPTION The 74AHC/AHCT595 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT595 is an 8-stage serial shift register with a storage register and 3-state outputs. The s

8-bit serial-in/serial-out or parallel-out shift register with output latches

1. General description The 74AHC595; 74AHCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading

8-BIT SHIFT REGISTER WITH 8-BIT OUTPUT REGISTER

Description The 74AHC595 is an advanced high speed CMOS device. An eight bit shift register accepts data from the serial input (DS) on each positive transition of the shift register clock (STCP). When asserted low the reset function (MR) sets all shift register values to zero and is independ

8-BIT SHIFT REGISTER WITH 8-BIT OUTPUT REGISTER

Description The 74AHC595 is an advanced high speed CMOS device. An eight bit shift register accepts data from the serial input (DS) on each positive transition of the shift register clock (STCP). When asserted low the reset function (MR) sets all shift register values to zero and is independ

8-BIT SHIFT REGISTER WITH 8-BIT OUTPUT REGISTER

Description The 74AHC595 is an advanced high speed CMOS device. An eight bit shift register accepts data from the serial input (DS) on each positive transition of the shift register clock (STCP). When asserted low the reset function (MR) sets all shift register values to zero and is independ

8-BIT SHIFT REGISTER WITH 8-BIT OUTPUT REGISTER

Description The 74AHC595 is an advanced high speed CMOS device. An eight bit shift register accepts data from the serial input (DS) on each positive transition of the shift register clock (STCP). When asserted low the reset function (MR) sets all shift register values to zero and is independ

NPN general-purpose double transistors output latches; 3-state

NPN general-purpose double transistors output latches; 3-state

8-bit serial-in/serial-out or parallel-out shift register with output latches

文件：794.74 Kbytes Page：22 Pages

封装/外壳：16-VFQFN 裸露焊盘 功能：串行至并行，串行 包装：管件 描述：IC SHIFT REGISTER 8BIT 16DHVQFN 集成电路（IC） 移位寄存器

NPN general-purpose double transistors output latches; 3-state

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：串行至并行，串行 包装：管件 描述：IC 8BIT SRL SHFT REGISTER 16SOIC 集成电路（IC） 移位寄存器

8-bit serial-in/serial-out or parallel-out shift register with output latches

文件：794.74 Kbytes Page：22 Pages

NPN general-purpose double transistors output latches; 3-state

8-bit serial-in/serial-out or parallel-out shift register with output latches

文件：794.74 Kbytes Page：22 Pages

8-bit serial-in/serial-out or parallel-out shift register with output latches

文件：794.74 Kbytes Page：22 Pages

8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS

文件：163.94 Kbytes Page：17 Pages

8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS

文件：163.94 Kbytes Page：17 Pages

8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS

文件：163.94 Kbytes Page：17 Pages