SNx4AC74 Dual Positive-Edge-Triggered D-Type Flip-Flops with Clear and Preset

1 Features • 2V to 6V VCC operation • Inputs accept voltages to 6V • Maximum tpd of 10ns at 5V 2 Applications • Convert a momentary switch to a toggle switch • Divide a clock signal by 2 or 4 3 Description The ’AC74 devices are dual positive-edge-triggered D-type flip-flops.

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

文件：1.14809 Mbytes Page：22 Pages

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

文件：542.71 Kbytes Page：17 Pages

封装/外壳：14-SSOP（0.209"，5.30mm 宽） 功能：设置（预设）和复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE DUAL 1BIT 14SSOP 集成电路（IC） 触发器

SNx4AC74 Dual Positive-Edge-Triggered D-Type Flip-Flops with Clear and Preset

1 Features • 2V to 6V VCC operation • Inputs accept voltages to 6V • Maximum tpd of 10ns at 5V 2 Applications • Convert a momentary switch to a toggle switch • Divide a clock signal by 2 or 4 3 Description The ’AC74 devices are dual positive-edge-triggered D-type flip-flops.

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

文件：542.71 Kbytes Page：17 Pages

Dual D?뭈ype Positive Edge?뭈riggered Flip?묯lop

Dual D−Type Positive Edge−Triggered Flip−Flop The MC74AC74/74ACT74 is a dual D−type flip−flop with Asynchronous Clear and Set inputs and complementary (Q,Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at

Dual D-Type Positive Edge-Triggered Flip-Flop

General Description The AC/ACT74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and i

Dual D-Type Positive Edge-Triggered Flip-Flop

General Description The AC/ACT74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is

DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR

文件：97.56 Kbytes Page：11 Pages

Dual D-Type Positive Edge-Triggered Flip-Flop

文件：111.59 Kbytes Page：10 Pages