18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

Members of the Texas Instruments WidebusE Family State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation High-Impedance State During Power Up and Power Down ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R

18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

Members of the Texas Instruments WidebusE Family State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation High-Impedance State During Power Up and Power Down ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R

18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

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18-bit bus interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ABT16823A 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • Two sets of high speed parallel registers with positive edge

18-bit bus interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ABT16823A 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • Two sets of high speed parallel registers with positive edge

18-bit bus interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ABT16823A 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • Two sets of high speed parallel registers with positive edge

18-bit bus interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ABT16823A 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • Two sets of high speed parallel registers with positive edge