LVDS SERDES RECEIVER

FEATURES · 3:21 Data Channel Compression at up to 1.428 Gigabits/s Throughput · Suited for Point-to-Point Subsystem Communication With Very Low EMI · 3 Data Channels and Clock Low-Voltage Differential Channels in and 21 Data and Clock Low-Voltage TTL Channels Out · Operates From a Single 3

LVDS SERDES RECEIVER

FEATURES · 3:21 Data Channel Compression at up to 1.428 Gigabits/s Throughput · Suited for Point-to-Point Subsystem Communication With Very Low EMI · 3 Data Channels and Clock Low-Voltage Differential Channels in and 21 Data and Clock Low-Voltage TTL Channels Out · Operates From a Single 3

封装/外壳：48-TFSOP（0.240"，6.10mm 宽） 功能：解串器 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC LVDS SERDES RECEIVER 48-TSSOP 集成电路（IC） 串行器，解串器

LVDS SERDES RECEIVER

文件：340.98 Kbytes Page：17 Pages

LVDS SERDES RECEIVER

FEATURES · 3:21 Data Channel Compression at up to 1.428 Gigabits/s Throughput · Suited for Point-to-Point Subsystem Communication With Very Low EMI · 3 Data Channels and Clock Low-Voltage Differential Channels in and 21 Data and Clock Low-Voltage TTL Channels Out · Operates From a Single 3

LVDS SERDES RECEIVER

FEATURES · 3:21 Data Channel Compression at up to 1.428 Gigabits/s Throughput · Suited for Point-to-Point Subsystem Communication With Very Low EMI · 3 Data Channels and Clock Low-Voltage Differential Channels in and 21 Data and Clock Low-Voltage TTL Channels Out · Operates From a Single 3

LVDS SERDES RECEIVER

文件：340.98 Kbytes Page：17 Pages

LVDS SERDES RECEIVER

文件：188.72 Kbytes Page：14 Pages

LVDS SERDES RECEIVER

FEATURES · 3:21 Data Channel Compression at up to 1.428 Gigabits/s Throughput · Suited for Point-to-Point Subsystem Communication With Very Low EMI · 3 Data Channels and Clock Low-Voltage Differential Channels in and 21 Data and Clock Low-Voltage TTL Channels Out · Operates From a Single 3

LVDS SERDES RECEIVER

FEATURES · 3:21 Data Channel Compression at up to 1.428 Gigabits/s Throughput · Suited for Point-to-Point Subsystem Communication With Very Low EMI · 3 Data Channels and Clock Low-Voltage Differential Channels in and 21 Data and Clock Low-Voltage TTL Channels Out · Operates From a Single 3

LVDS SERDES RECEIVER

FEATURES · 3:21 Data Channel Compression at up to 1.428 Gigabits/s Throughput · Suited for Point-to-Point Subsystem Communication With Very Low EMI · 3 Data Channels and Clock Low-Voltage Differential Channels in and 21 Data and Clock Low-Voltage TTL Channels Out · Operates From a Single 3

LVDS SERDES RECEIVER

FEATURES · 3:21 Data Channel Compression at up to 1.428 Gigabits/s Throughput · Suited for Point-to-Point Subsystem Communication With Very Low EMI · 3 Data Channels and Clock Low-Voltage Differential Channels in and 21 Data and Clock Low-Voltage TTL Channels Out · Operates From a Single 3

LVDS SERDES RECEIVER

FEATURES · 3:21 Data Channel Compression at up to 1.428 Gigabits/s Throughput · Suited for Point-to-Point Subsystem Communication With Very Low EMI · 3 Data Channels and Clock Low-Voltage Differential Channels in and 21 Data and Clock Low-Voltage TTL Channels Out · Operates From a Single 3

LVDS SERDES RECEIVER

文件：340.98 Kbytes Page：17 Pages

封装/外壳：48-TFSOP（0.240"，6.10mm 宽） 功能：解串器 包装：卷带（TR） 描述：IC LVDS SERDES RECEIVER 48-TSSOP 集成电路（IC） 串行器，解串器

LVDS SERDES RECEIVER

文件：188.72 Kbytes Page：14 Pages