丝印：SN65LVDS96；LVDS SERDES RECEIVER

FEATURES · 3:21 Data Channel Compression at up to 1.428 Gigabits/s Throughput · Suited for Point-to-Point Subsystem Communication With Very Low EMI · 3 Data Channels and Clock Low-Voltage Differential Channels in and 21 Data and Clock Low-Voltage TTL Channels Out · Operates From a Single 3

LVDS SERDES RECEIVER

FEATURES · 3:21 Data Channel Compression at up to 1.428 Gigabits/s Throughput · Suited for Point-to-Point Subsystem Communication With Very Low EMI · 3 Data Channels and Clock Low-Voltage Differential Channels in and 21 Data and Clock Low-Voltage TTL Channels Out · Operates From a Single 3

LVDS SERDES RECEIVER

FEATURES · 3:21 Data Channel Compression at up to 1.428 Gigabits/s Throughput · Suited for Point-to-Point Subsystem Communication With Very Low EMI · 3 Data Channels and Clock Low-Voltage Differential Channels in and 21 Data and Clock Low-Voltage TTL Channels Out · Operates From a Single 3

LVDS SERDES RECEIVER

FEATURES · 3:21 Data Channel Compression at up to 1.428 Gigabits/s Throughput · Suited for Point-to-Point Subsystem Communication With Very Low EMI · 3 Data Channels and Clock Low-Voltage Differential Channels in and 21 Data and Clock Low-Voltage TTL Channels Out · Operates From a Single 3

LVDS SERDES RECEIVER

文件：188.72 Kbytes Page：14 Pages

LVDS SERDES RECEIVER

文件：340.98 Kbytes Page：17 Pages

LVDS SERDES RECEIVER

文件：188.72 Kbytes Page：14 Pages