512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent 512 × 36 Clocked FIFOs Buffering Data in Opposite Directions Mailbox-Bypass Register for Each FIFO Programmable Almost-Full and Almost-Empty Flags Microprocessor Interface Control Logic IRA, ORA, AEA, and AFA Flag

512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent 512 × 36 Clocked FIFOs Buffering Data in Opposite Directions Mailbox-Bypass Register for Each FIFO Programmable Almost-Full and Almost-Empty Flags Microprocessor Interface Control Logic IRA, ORA, AEA, and AFA Flag

512 횞 36 횞 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

文件：383.79 Kbytes Page：25 Pages

512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent 512 × 36 Clocked FIFOs Buffering Data in Opposite Directions Mailbox-Bypass Register for Each FIFO Programmable Almost-Full and Almost-Empty Flags Microprocessor Interface Control Logic IRA, ORA, AEA, and AFA Flag

512 횞 36 횞 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

文件：383.79 Kbytes Page：25 Pages