LVPECL Low Jitter Clock Buffer

1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR

Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t

Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs

Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t

Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs

Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t

1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR

Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t

1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR

Features  Supports single-ended or differential input clock signals  Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs  Provides signal level translation Differential to single-ended Single-ended to differential Differential to dif

1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR

Features  Supports single-ended or differential input clock signals  Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs  Provides signal level translation Differential to single-ended Single-ended to differential Differential to dif

The Si5330 Clock Buffer datasheet v1.0 is now available

文件：41.28 Kbytes Page：1 Pages

The Si5330 Clock Buffer datasheet v1.0 is now available

文件：41.28 Kbytes Page：1 Pages

封装/外壳：24-VFQFN 裸露焊盘 包装：托盘 描述：IC CLK BUFFER 1:4 710MHZ 24QFN 集成电路（IC） 时钟缓冲器，驱动器

封装/外壳：24-VFQFN 裸露焊盘 包装：卷带（TR） 描述：IC CLK BUFFER 1:4 LVPECL 24QFN 集成电路（IC） 时钟缓冲器，驱动器

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