DB1200ZL 12-OUTPUT PCIE GEN 3 BUFFER

Features  Twelve 0.7 V low-power, pushpull, HCSL-compatible PCIe Gen 3 outputs  Individual OE HW pins for each output clock  100 MHz /133 MHz PLL operation, supports PCIe and QPI  PLL bandwidth SW SMBUS programming overrides the latch value from HW pin  9 selectable SMBUS addresse

PCIe Fanout/Zero-Delay Buffer

The Si53112 is a 1 : 12 PCIe Fanout/Zero-Delay Buffer that meets all of the performance requirements of the Intel DB1900Z specification. The device is optimized for distributing 12  reference clocks for Intel® QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/ Gen 3, SAS, SATA and Intel Scalable

DB1200ZL 12-OUTPUT PCIE GEN 3 BUFFER

文件：1.46181 Mbytes Page：35 Pages

DB1200ZL 12-OUTPUT PCIE GEN 3 BUFFER

Features  Twelve 0.7 V low-power, pushpull, HCSL-compatible PCIe Gen 3 outputs  Individual OE HW pins for each output clock  100 MHz /133 MHz PLL operation, supports PCIe and QPI  PLL bandwidth SW SMBUS programming overrides the latch value from HW pin  9 selectable SMBUS addresse

DB1200ZL 12-OUTPUT PCIE GEN 3 BUFFER

Features  Twelve 0.7 V low-power, pushpull, HCSL-compatible PCIe Gen 3 outputs  Individual OE HW pins for each output clock  100 MHz /133 MHz PLL operation, supports PCIe and QPI  PLL bandwidth SW SMBUS programming overrides the latch value from HW pin  9 selectable SMBUS addresse

DB1200ZL 12-OUTPUT PCIE GEN 3 BUFFER

Features  Twelve 0.7 V low-power, pushpull, HCSL-compatible PCIe Gen 3 outputs  Individual OE HW pins for each output clock  100 MHz /133 MHz PLL operation, supports PCIe and QPI  PLL bandwidth SW SMBUS programming overrides the latch value from HW pin  9 selectable SMBUS addresse

DB1200ZL 12-OUTPUT PCIE GEN 3 BUFFER

Features  Twelve 0.7 V low-power, pushpull, HCSL-compatible PCIe Gen 3 outputs  Individual OE HW pins for each output clock  100 MHz /133 MHz PLL operation, supports PCIe and QPI  PLL bandwidth SW SMBUS programming overrides the latch value from HW pin  9 selectable SMBUS addresse

DB1200ZL 12-OUTPUT PCIE GEN 3 BUFFER

Features  Twelve 0.7 V low-power, pushpull, HCSL-compatible PCIe Gen 3 outputs  Individual OE HW pins for each output clock  100 MHz /133 MHz PLL operation, supports PCIe and QPI  PLL bandwidth SW SMBUS programming overrides the latch value from HW pin  9 selectable SMBUS addresse

封装/外壳：64-VFQFN 裸露焊盘 包装：卷带（TR） 描述：IC BUFFER ZDB PCIE 1:12 64-QFN 集成电路（IC） 应用特定时钟/定时

DB1200ZL 12-OUTPUT PCIE GEN 3 BUFFER

文件：1.43783 Mbytes Page：34 Pages

封装/外壳：64-VFQFN 裸露焊盘 包装：管件 描述：1:12 LOW-POWER PCIE FANOUT/ZERO- 集成电路（IC） 应用特定时钟/定时

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