9 Channel Bus LVDS Transceiver w/ Boundary SCAN

文件：701.97 Kbytes Page：13 Pages

9 Channel Bus LVDS Transceiver w/ Boundary SCAN

文件：352.62 Kbytes Page：14 Pages

SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN

1FEATURES 2• IEEE 1149.1 (JTAG) Compliant • Bus LVDS Signaling • Low Power CMOS Design • High Signaling Rate Capability (Above 100 Mbps) • 0.1V to 2.3V Common Mode Range for VID = 200mV • ±100 mV Receiver Sensitivity • Supports Open and Terminated Failsafe on Port Pins • 3.3V Operation

SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN

1FEATURES 2• IEEE 1149.1 (JTAG) Compliant • Bus LVDS Signaling • Low Power CMOS Design • High Signaling Rate Capability (Above 100 Mbps) • 0.1V to 2.3V Common Mode Range for VID = 200mV • ±100 mV Receiver Sensitivity • Supports Open and Terminated Failsafe on Port Pins • 3.3V Operation

SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN

1FEATURES 2• IEEE 1149.1 (JTAG) Compliant • Bus LVDS Signaling • Low Power CMOS Design • High Signaling Rate Capability (Above 100 Mbps) • 0.1V to 2.3V Common Mode Range for VID = 200mV • ±100 mV Receiver Sensitivity • Supports Open and Terminated Failsafe on Port Pins • 3.3V Operation

SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN

1FEATURES 2• IEEE 1149.1 (JTAG) Compliant • Bus LVDS Signaling • Low Power CMOS Design • High Signaling Rate Capability (Above 100 Mbps) • 0.1V to 2.3V Common Mode Range for VID = 200mV • ±100 mV Receiver Sensitivity • Supports Open and Terminated Failsafe on Port Pins • 3.3V Operation

SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN

文件：613.82 Kbytes Page：19 Pages

封装/外壳：64-LQFP 包装：管件 描述：IC TRANSCEIVER HALF 9/9 64TQFP 集成电路（IC） 驱动器，接收器，收发器

SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN

文件：613.82 Kbytes Page：19 Pages

封装/外壳：64-LQFP 包装：卷带（TR） 描述：IC TRANSCEIVER HALF 9/9 64TQFP 集成电路（IC） 驱动器，接收器，收发器

DS92LV090A 9 Channel Bus LVDS Transceiver

1FEATURES 2• Bus LVDS Signaling • 3.2 Nanosecond Propagation Delay Max • Chip to Chip Skew ±800ps • Low Power CMOS Design • High Signaling Rate Capability (Above 100 Mbps) • 0.1V to 2.3V Common Mode Range for VID = 200mV • ±100 mV Receiver Sensitivity • Supports Open and Terminated Fails

9 Channel Bus LVDS Transceiver

文件：291.54 Kbytes Page：12 Pages

9 Channel Bus LVDS Transceiver

文件：170.26 Kbytes Page：9 Pages

9 Channel Bus LVDS Transceiver

文件：938.27 Kbytes Page：16 Pages

DS92LV090AEP 9 Channel Bus LVDS Transceiver

文件：308.24 Kbytes Page：14 Pages