DS92LV090A 9 Channel Bus LVDS Transceiver

1FEATURES 2• Bus LVDS Signaling • 3.2 Nanosecond Propagation Delay Max • Chip to Chip Skew ±800ps • Low Power CMOS Design • High Signaling Rate Capability (Above 100 Mbps) • 0.1V to 2.3V Common Mode Range for VID = 200mV • ±100 mV Receiver Sensitivity • Supports Open and Terminated Fails

9 通道总线 LVDS 收发器

The DS92LV090A is one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates from a single 3.3V power supply and includes nine differential line drivers and nine receivers. To minimize bus loading, the d • Bus LVDS Signaling\n• 3.2 Nanosecond Propagation Delay Max\n• Chip to Chip Skew ±800ps\n• Low Power CMOS Design\n• High Signaling Rate Capability (Above 100 Mbps)\n• 0.1V to 2.3V Common Mode Range for VID = 200mV\n• ±100 mV Receiver Sensitivity\n• Supports Open and Terminated Failsafe on Port Pins;

9 Channel Bus LVDS Transceiver

文件：170.26 Kbytes Page：9 Pages

9 Channel Bus LVDS Transceiver

文件：291.54 Kbytes Page：12 Pages

9 Channel Bus LVDS Transceiver

文件：938.27 Kbytes Page：16 Pages

丝印代码：DS92LV090ATVEH；DS92LV090A 9 Channel Bus LVDS Transceiver

1FEATURES 2• Bus LVDS Signaling • 3.2 Nanosecond Propagation Delay Max • Chip to Chip Skew ±800ps • Low Power CMOS Design • High Signaling Rate Capability (Above 100 Mbps) • 0.1V to 2.3V Common Mode Range for VID = 200mV • ±100 mV Receiver Sensitivity • Supports Open and Terminated Fails

丝印代码：DS92LV090ATVEH；DS92LV090A 9 Channel Bus LVDS Transceiver

1FEATURES 2• Bus LVDS Signaling • 3.2 Nanosecond Propagation Delay Max • Chip to Chip Skew ±800ps • Low Power CMOS Design • High Signaling Rate Capability (Above 100 Mbps) • 0.1V to 2.3V Common Mode Range for VID = 200mV • ±100 mV Receiver Sensitivity • Supports Open and Terminated Fails

丝印代码：DS92LV090ATVEH；DS92LV090A 9 Channel Bus LVDS Transceiver

1FEATURES 2• Bus LVDS Signaling • 3.2 Nanosecond Propagation Delay Max • Chip to Chip Skew ±800ps • Low Power CMOS Design • High Signaling Rate Capability (Above 100 Mbps) • 0.1V to 2.3V Common Mode Range for VID = 200mV • ±100 mV Receiver Sensitivity • Supports Open and Terminated Fails

丝印代码：DS92LV090ATVEH；DS92LV090A 9 Channel Bus LVDS Transceiver

1FEATURES 2• Bus LVDS Signaling • 3.2 Nanosecond Propagation Delay Max • Chip to Chip Skew ±800ps • Low Power CMOS Design • High Signaling Rate Capability (Above 100 Mbps) • 0.1V to 2.3V Common Mode Range for VID = 200mV • ±100 mV Receiver Sensitivity • Supports Open and Terminated Fails

丝印代码：DS92LV090ATVEH；DS92LV090A 9 Channel Bus LVDS Transceiver

1FEATURES 2• Bus LVDS Signaling • 3.2 Nanosecond Propagation Delay Max • Chip to Chip Skew ±800ps • Low Power CMOS Design • High Signaling Rate Capability (Above 100 Mbps) • 0.1V to 2.3V Common Mode Range for VID = 200mV • ±100 mV Receiver Sensitivity • Supports Open and Terminated Fails

丝印代码：DS92LV090ATVEH；DS92LV090A 9 Channel Bus LVDS Transceiver

1FEATURES 2• Bus LVDS Signaling • 3.2 Nanosecond Propagation Delay Max • Chip to Chip Skew ±800ps • Low Power CMOS Design • High Signaling Rate Capability (Above 100 Mbps) • 0.1V to 2.3V Common Mode Range for VID = 200mV • ±100 mV Receiver Sensitivity • Supports Open and Terminated Fails

DS92LV090A 9 Channel Bus LVDS Transceiver

1FEATURES 2• Bus LVDS Signaling • 3.2 Nanosecond Propagation Delay Max • Chip to Chip Skew ±800ps • Low Power CMOS Design • High Signaling Rate Capability (Above 100 Mbps) • 0.1V to 2.3V Common Mode Range for VID = 200mV • ±100 mV Receiver Sensitivity • Supports Open and Terminated Fails

9 Channel Bus LVDS Transceiver

文件：291.54 Kbytes Page：12 Pages

9 Channel Bus LVDS Transceiver

文件：938.27 Kbytes Page：16 Pages

DS92LV090AEP 9 Channel Bus LVDS Transceiver

文件：308.24 Kbytes Page：14 Pages

9 Channel Bus LVDS Transceiver

文件：291.54 Kbytes Page：12 Pages

9 Channel Bus LVDS Transceiver

文件：170.26 Kbytes Page：9 Pages

9 Channel Bus LVDS Transceiver

文件：938.27 Kbytes Page：16 Pages

封装/外壳：64-LQFP 包装：管件 描述：IC TRANSCEIVER HALF 9/9 64TQFP 集成电路（IC） 驱动器，接收器，收发器

9 Channel Bus LVDS Transceiver

文件：938.27 Kbytes Page：16 Pages

9 Channel Bus LVDS Transceiver

文件：938.27 Kbytes Page：16 Pages

封装/外壳：64-LQFP 包装：卷带（TR） 描述：IC TRANSCEIVER HALF 9/9 64TQFP 集成电路（IC） 驱动器，接收器，收发器

9 Channel Bus LVDS Transceiver

文件：938.27 Kbytes Page：16 Pages

9 Channel Bus LVDS Transceiver w/ Boundary SCAN

文件：701.97 Kbytes Page：13 Pages

9 Channel Bus LVDS Transceiver with 1149.1 Access

文件：30.13 Kbytes Page：1 Pages

9 Channel Bus LVDS Transceiver w/ Boundary SCAN

文件：701.97 Kbytes Page：13 Pages

9 Channel Bus LVDS Transceiver w/ Boundary SCAN

文件：701.97 Kbytes Page：13 Pages