Buck or Buck-Boost (Inverting) Current Mode Controller

Description The SC4508A is a low voltage current mode switching regulator controller that drives a P-channel power MOSFET with programmable switching frequency. It can be configured in either buck or buck boost (inverting) con verters. The converters can be operated from 2.7V to 15V input volta

封装/外壳：12-VQFN 裸露焊盘 功能：降压，升压/降压 包装：卷带（TR） 描述：IC REG CTRLR BUCK/BCK-BST 12MLPQ 集成电路（IC） PMIC - 稳压器 - DC DC 开关式控制器

封装/外壳：12-VQFN 裸露焊盘 功能：降压，升压/降压 包装：卷带（TR） 描述：IC REG CTRLR BUCK/BCK-BST 12MLPQ 集成电路（IC） DC-DC 开关控制器

Silicon Diffused Power Transistor

GENERAL DESCRIPTION Enhanced performance, new generation, high-voltage, high-speed switching npn transistor in a plastic envelope intended for use in horizontal deflection circuits of colour television receivers and p.c monitors. Features exceptional tolerance to base drive and collector current

Silicon Diffused Power Transistor

GENERAL DESCRIPTION Enhanced performance, new generation, high-voltage, high-speed switching npn transistor with an integrated damper diode in a plastic full-pack envelope intended for use in horizontal deflection circuits of colour television receivers. Features exceptional tolerance to

Dual 4-bit latch

DESCRIPTION The HEF4508B is a dual 4-bit latch, which consists of two identical independent 4-bit latches with separate strobe (ST), master reset (MR), output-enable input (EO) and 3-state outputs (O). With the ST input in the HIGH state, the data on the D inputs appear at the corresponding outp

Dual 4-bit latch

DESCRIPTION The HEF4508B is a dual 4-bit latch, which consists of two identical independent 4-bit latches with separate strobe (ST), master reset (MR), output-enable input (EO) and 3-state outputs (O). With the ST input in the HIGH state, the data on the D inputs appear at the corresponding outp

Dual 4-bit latch

DESCRIPTION The HEF4508B is a dual 4-bit latch, which consists of two identical independent 4-bit latches with separate strobe (ST), master reset (MR), output-enable input (EO) and 3-state outputs (O). With the ST input in the HIGH state, the data on the D inputs appear at the corresponding outp