Low Cost DDR Phase Lock Loop Zero Delay Buffer

Description Output Features DDR Zero Delay Clock Buffer • Low skew, low jitter PLL clock driver • I2C for functional and output control • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • 3.3V tolerant CLK_INT input Key Specifications • PEAK - PEAK jitt

Low Cost DDR Phase Lock Loop Zero Delay Buffer

Product Description/Features: • Low skew, low jitter PLL clock driver • I2C for functional and output control • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • 3.3V tolerant CLK_INT input Switching Characteristics: • PEAK - PEAK jitter (66MHz):

Low Cost DDR Phase Lock Loop Zero Delay Buffer

Product Description/Features: • Low skew, low jitter PLL clock driver • I2C for functional and output control • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • 3.3V tolerant CLK_INT input Switching Characteristics: • PEAK - PEAK jitter (66MHz):

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