Description

The 8V19N474 is a fully integrated FemtoClock NG Jitter Attenuator

and Clock Synthesizer designed as a high-performance clock

solution for conditioning and frequency/phase management of

10/40/100/400 Gigabit-Ethernet line cards. The device delivers

excellent phase noise performance as required to drive physical

layer devices, and provides the clean clock frequencies

(e.g., 625MHz, 500MHz, 312.5MHz, 250MHz, 156.25MHz, and

125MHz).

A two-stage PLL architecture supports both jitter attenuation and

frequency multiplication. The first stage PLL is the jitter attenuator

and uses an external VCXO for best possible phase noise

characteristics. The second stage PLL locks on the VCXO-PLL

output signal and synthesizes the target frequency. This PLL has a

VCO circuit at 2500MHz.

The 8V19N474 generates the output clock signals from the VCO by

frequency division. Five independent frequency dividers are

available: four support integer-divider ratios and one integer as well

as fractional-divider ratios. Delay circuits can be used for achieving

alignment and controlled phase delay between clock signals. The

two redundant inputs are monitored for activity.

Four selectable clock switching modes are provided to handle clock

input failure scenarios. Auto-lock, individually programmable output

frequency dividers, and phase adjustment capabilities are added for

additional flexibility. The 8V19N474 is configured through an SPI

interface and reports lock and signal loss status in internal registers

and via a lock detect (LOCK) output. Internal status bit changes can

also be reported via the nINT output. The device is ideal for driving

converter circuits in wireless infrastructure, radar/imaging, and

instrumentation/medical applications. The device is a member of the

high-performance clock family from IDT.

Features

▪ High-performance clock RF-PLL

— Optimized for low phase noise: -153dBc/Hz (1MHz offset;

156.25MHz clock)

— Integrated phase noise (12kHz–20MHz) of 75fs RMS typical

▪ Dual-PLL architecture

— 1st-PLL stage with external VCXO for clock jitter attenuation

— 2nd-PLL stage with internal FemtoClock NG PLL at 2500MHz

▪ 6 output banks with a total of 12 outputs, organized in:

— Two clock banks with one integer frequency divider and three

differential outputs

— Two clock banks with one integer frequency divider and two

differential outputs

— One clock bank with one fractional output divider and one

differential output

— One VCXO-PLL output bank with one selectable LVDS/two

LVCMOS outputs

▪ Four output banks contain a phase delay circuit with steps of the

VCO clock period (400ps)

▪ Supported clock output frequencies include:

— From the integer dividers: 2500MHz, 1250MHz, 625MHz,

500MHz, 312.5MHz, 250MHz, 156.25MHz, and 125MHz

— From the fractional divider: 80–300MHz

▪ Low-power LVPECL/LVDS outputs support configurable signal

amplitude, DC and AC coupling and LVPECL, LVDS line

terminations techniques

▪ Redundant input clock architecture

— Two inputs

— Individual input signal monitor

— Digital holdover

— Manual and automatic clock selection

— Hitless switching

▪ Status monitoring and fault reporting

— Input signal status

— Holdover and reference loss status

— Lock status with one status pin

— Maskable status interrupt pin

▪ Voltage supply:

— Device core supply voltage: 3.3V

— Output supply voltage: 3.3V, 2.5V, or 1.8V

— SPI control I/O voltage: 1.8V or 3.3V (selectable),

3.3V tolerant inputs when set to 1.8V

▪ Package: 8 × 8 mm 81-FPBGA, RoHS 6/6

▪ Temperature range: -40°C to +85°C