Description

The 8V19N472 is a fully integrated FemtoClock NG Jitter Attenuator

and Clock Synthesizer designed as a high-performance clock

solution for conditioning and frequency/phase management of

wireless base station radio equipment boards. The device is

optimized to deliver excellent phase noise performance as required

in GSM, WCDMA, LTE, and LTE-A radio board implementations.

A two-stage PLL architecture supports both jitter attenuation and

frequency multiplication. The first stage PLL is the jitter attenuator

and uses an external VCXO for best possible phase noise

characteristics. The second stage PLL locks on the VCXO-PLL

output signal and synthesizes the target frequency. This PLL has two

VCO circuits at 2949.12MHz and 2400–2500MHz, respectively, for

enhanced frequency flexibility.

The device generates the output clock signals from the selected

VCO by frequency division. Five independent frequency dividers are

available, four support integer-divider ratios and one integer as well

as fractional-divider ratios. Delay circuits can be used for achieving

alignment and controlled phase delay between clock signals. The

two redundant inputs are monitored for activity. Four selectable clock

switching modes are provided to handle clock input failure scenarios.

Auto-lock, individually programmable output frequency dividers, and

phase adjustment capabilities are added for flexibility.

The 8V19N472 is configured through an SPI interface and reports

lock and signal loss status in internal registers and via a lock detect

(LOCK) output. Internal status bit changes can also be reported via

the nINT output. The device is ideal for driving converter circuits in

wireless infrastructure, radar/imaging, and instrumentation/medical

applications. The device is a member of the high-performance clock

family from IDT.

Features

▪ High-performance clock RF-PLL

▪ Optimized for low phase noise: <-150dBc/Hz (1MHz offset;

245.76MHz clock)

▪ Dual-PLL architecture

— 1st-PLL stage with external VCXO for clock jitter attenuation

— 2nd-PLL stage with internal FemtoClockNG PLL at selectable

2949.12MHz and MHz (2400–2500MHz) VCO frequency

▪ Six output banks with a total of 12 outputs, organized in:

— Two clock banks with one integer frequency divider and three

differential outputs

— Two clock banks with one integer frequency divider and two

differential outputs

— One clock bank with one fractional output divider and one

differential output

— One VCXO-PLL output bank with one selectable LVDS/two

LVCMOS outputs

▪ Supported clock output frequencies include:

— From VCO-0: 2949.12, 1474.56, 983.04, 491.52, 368.64,

122.88MHz

— From VCO-1: 2457.6, 1228.8, 614.4, 307.2, 153.6, 76.8MHz

— From the fractional output divider: 80 – 300MHz

▪ Clock channels with integer output divider contain a phase delay

circuit with 512 steps of half of the selected VCO period

▪ Low-power LVPECL/LVDS outputs support configurable signal

amplitude, DC and AC coupling and LVPECL, LVDS line

terminations techniques

▪ Redundant input clock architecture

— Two inputs with an individual input signal monitor

— Digital holdover

— Manual and automatic clock selection

— Hitless switching

▪ Status monitoring and fault reporting

— Input signal status

— Hold-over and reference loss status

— Lock status with one status pin

— Maskable status interrupt pin

▪ Voltage supply:

— Device core supply voltage: 3.3V

— Output supply voltage: 3.3V, 2.5V, or 1.8V

— SPI control I/O voltage: 1.8V or 3.3V (selectable),

3.3V tolerant inputs when set to 1.8V

▪ Package: 81-FPBGA (8  8mm, 0.8 mm ball pitch)

▪ Temperature range: -40°C to +85°C