Switching, Inverter Circuit, Interface Circuit and Driver Circuit Applications

Switching, Inverter Circuit, Interface Circuit and Driver Circuit Applications Ultra-small package, suited to very high density mounting Incorporating a bias resistor into the transistor reduces the number of parts, so enabling the manufacture of ever more compact equipment and lowering

Bias resistor built-in transistor (BRT)

Application Scope：General-purpose\nPolarity：PNP\nInternal Connection：Single\nComplementary Product：RN1104MFV\nAEC-Q101：Conform(*)\nRoHS Compatible Product(s) (#)：Available\nAssembly bases：日本 / 泰国 Collector Current IC -0.1 A \nCollector-emitter voltage VCEO -50 V ;

封装/外壳：SOT-723 包装：剪切带（CT）带盒（TB） 描述：TRANS PREBIAS PNP 50V 0.1A VESM 分立半导体产品 晶体管 - 双极（BJT）- 单，预偏置

封装/外壳：SOT-723 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：AUTO AEC-Q PNP Q1BSR=47K, Q1BER= 分立半导体产品 晶体管 - 双极（BJT）- 单，预偏置

256KB and 512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms

The MPC2104/5/6/7 are designed to provide burstable, high performance L2 cache for the PowerPC 60x microprocessor family in conformance with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware Reference Platform (CHRP) specifications. These products utilize synchronous or asynchr

256KB/512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms

The MPC2104P (256KB) and MPC2105P (512KB) are designed to provide burstable, high performance L2 cache for the PowerPC 60x microprocessor family in conformance with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware Reference Platform (CHRP) specifications. All of these cache m

3V AM/FM 1 CHIP TUNER IC (FOR DIGITAL TUNING SYSTEM)

TA2104BN, TA2104BFN are AM/FM 1 chip tuner ICs, which are designed for portable Radios and 3V Head phone Radios.

P-Channel Enhancement-Mode Vertical DMOS FETs

General Description This low threshold enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and with the high in

P-Channel Enhancement-Mode Vertical DMOS FETs

General Description This low threshold enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and with the high in