Dual 2-to-4-line Decoders / Demultiplexers

Description The RD74LVC139B has two independent two-to-four-line decoders each with a single active low enable input in a 16 pin package. Data on the select inputs cause one of the four normally high outputs to go low. Low voltage and high-speed operation is suitable at the battery drive product

Dual 2-to-4-line Decoders / Demultiplexers

Dual 2-to-4-line Decoders / Demultiplexers

Description The RD74LVC139B has two independent two-to-four-line decoders each with a single active low enable input in a 16 pin package. Data on the select inputs cause one of the four normally high outputs to go low. Low voltage and high-speed operation is suitable at the battery drive product

Dual 2-to-4-line Decoders / Demultiplexers

Description The RD74LVC139B has two independent two-to-four-line decoders each with a single active low enable input in a 16 pin package. Data on the select inputs cause one of the four normally high outputs to go low. Low voltage and high-speed operation is suitable at the battery drive product

Dual 2-to-4-line Decoders / Demultiplexers

文件：116.21 Kbytes Page：10 Pages

General-Purpose Logics

Dual 2-to-4-line Decoders / Demultiplexers

文件：116.21 Kbytes Page：10 Pages

General-Purpose Logics

Dual 2-to-4-line Decoders / Demultiplexers

文件：116.21 Kbytes Page：10 Pages

Dual 2-to-4 line decoder/demultiplexer

DESCRIPTION The 74LVC139 is a low-voltage, low-power, high-performance Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply voltage range of 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A • Inputs accept voltages up to 5.5 V • CMOS lo

Dual 2-to-4 line decoder/demultiplexer

1. General description The 74LVC139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-4 demulti

Dual 2-to-4 line decoder/demultiplexer

1. General description The 74LVC139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-4 demulti

Dual 2-to-4 line decoder/demultiplexer

1. General description The 74LVC139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-4 demulti

Dual 2-to-4 line decoder/demultiplexer

DESCRIPTION The 74LVC139 is a low-voltage, low-power, high-performance Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply voltage range of 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A • Inputs accept voltages up to 5.5 V • CMOS lo