3-to-8-line Decoder / Demultiplexer

Description The RD74LVC138B has three binary select inputs in a 16 pin package. If the device is enabled these inputs determine which one of the eight normally high outputs will go low. Two active low and one active high enables are provided to ease the cascading of decoders. Low voltage and hi

3-to-8-line Decoder / Demultiplexer

3-to-8-line Decoder / Demultiplexer

Description The RD74LVC138B has three binary select inputs in a 16 pin package. If the device is enabled these inputs determine which one of the eight normally high outputs will go low. Two active low and one active high enables are provided to ease the cascading of decoders. Low voltage and hi

3-to-8-line Decoder / Demultiplexer

Description The RD74LVC138B has three binary select inputs in a 16 pin package. If the device is enabled these inputs determine which one of the eight normally high outputs will go low. Two active low and one active high enables are provided to ease the cascading of decoders. Low voltage and hi

3-to-8-line Decoder / Demultiplexer

文件：100.7 Kbytes Page：10 Pages

General-Purpose Logics

3-to-8-line Decoder / Demultiplexer

文件：100.7 Kbytes Page：10 Pages

General-Purpose Logics

3-to-8-line Decoder / Demultiplexer

文件：100.7 Kbytes Page：10 Pages

3-to-8 line decoder/demultiplexer; inverting

1. General description The 74LVC138A decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The 74LVC138A features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable f

3-to-8 line decoder/demultiplexer; inverting

DESCRIPTION The 74LVC138A is a low-voltage, low-power, high-performance Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply voltage range of 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A • Inputs accept voltages up to 5.5 V • CMOS l

3-to-8 line decoder/demultiplexer; inverting

1. General description The 74LVC138A decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The 74LVC138A features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable f

3-to-8 line decoder/demultiplexer; inverting

DESCRIPTION The 74LVC138A is a low-voltage, low-power, high-performance Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply voltage range of 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A • Inputs accept voltages up to 5.5 V • CMOS l

3-to-8 line decoder/demultiplexer; inverting

文件：184.85 Kbytes Page：16 Pages