True low-power platform (66 μA/MHz, and 0.57 μA for operation with only RTC and LVD) for the general-purpose applications, with 1.6-V to 5.5-V operation, 16- to 512-Kbyte code flash memory, and 41 DMIPS at 32 MHz

1.1 Features Ultra-low power consumption technology  VDD = single power supply voltage of 1.6 to 5.5 V  HALT mode  STOP mode  SNOOZE mode RL78 CPU core  CISC architecture with 3-stage pipeline  Minimum instruction execution time: Can be changed from high speed (0.03125 μs: @ 32 MHz

True Low Power Platform

文件：1.74099 Mbytes Page：202 Pages

PG-FP5

文件：153.47 Kbytes Page：17 Pages

True Low Power Platform (as low as 66 ?쵡/MHz, and 0.60 ?쵡 for RTC LVD), 1.6 V to 5.5 V operation

文件：854.74 Kbytes Page：100 Pages

Low Power, High Function Microcontrollers for General Purpose Applications

Low Power, High Function Microcontrollers for General Purpose Applications

Low Power, High Function Microcontrollers for General Purpose Applications

True Low Power Platform

文件：1.74099 Mbytes Page：202 Pages

MSPM0H321x Mixed-Signal Microcontrollers

1 Features • Core – Arm® 32-bit Cortex®-M0+ CPU, frequency up to 32MHz • Operating characteristics – Extended temperature: –40°C to 125°C – Supply voltage range: 4.5V to 5.5V • Memories – Up to 64KB of flash – 8KB of SRAM • High-performance analog peripherals – One analog-to-digital con

MSPM0H321x Mixed-Signal Microcontrollers

1 Features • Core – Arm® 32-bit Cortex®-M0+ CPU, frequency up to 32MHz • Operating characteristics – Extended temperature: –40°C to 125°C – Supply voltage range: 4.5V to 5.5V • Memories – Up to 64KB of flash – 8KB of SRAM • High-performance analog peripherals – One analog-to-digital con

True low-power platform (66 μA/MHz, and 0.57 μA for operation with only RTC and LVD) for the general-purpose applications, with 1.6-V to 5.5-V operation, 16- to 512-Kbyte code flash memory, and 41 DMIPS at 32 MHz

1.1 Features Ultra-low power consumption technology  VDD = single power supply voltage of 1.6 to 5.5 V  HALT mode  STOP mode  SNOOZE mode RL78 CPU core  CISC architecture with 3-stage pipeline  Minimum instruction execution time: Can be changed from high speed (0.03125 μs: @ 32 MHz

N-Channel FREDFET

文件：197.49 Kbytes Page：4 Pages