CAN Controller

▪ Protocol : ISO 11898-1 compliant (standard and extended frames) ▪ Reception − Data frame and remote frame can be received. − Selectable receiving ID format. (only standard ID, only extended ID, or bothIDs) − Programmable one-shot reception function. − Selectable from overwrite mode (messa

CAN FD Controller Multi-channel type

This IP is CAN FD controller that is compliant with ISO 11898-1 (2015) Specifications. It embeds multiple CAN channels. 2,4,6 and 8 channel version are available. Each CAN channel can be configurable to CAN FD or classic CAN and transmits and receives both ID formats of messages, namely the sta

CAN FD Controller Single-channel type

This IP is CAN FD one channel version controller that is compliant with ISO 11898-1 (2015) Specifications. This CAN module embeds single CAN channel. This CAN module can be configurable to CAN FD or classic CAN, transmits and receives both ID formats of messages, namely the standard identifier

LVDS I/O Buffer

The LVDS I/O has driver and receiver of TSMC 16, 22, 28, 40nm and Samsung 14nm process. - Support LVDS specification is TIA/EIA-644-A. - LVDS driver and receiver support data rates up to 600Mbps to 1Gbps. - ESD, LatchUp compliant with AEC-Q100 for automotive. - Power supplies 1.8V±0.15V for IO

32-bit RISC CPU IP

▪ 32-bit internal data bus ▪ General purpose register file: − 16 32-bit general-purpose registers (and 8 32-bit shadow registers) − Seven 32-bit control registers − Four 32-bit system registers ▪ RISC type instruction set (with upward compatibility with SH-1, SH-2, SH-3, SH-4): − Instructi

General PWM Timer

32 bits timer counter x 8 channels - Counter operation(Saw-wave and Triangle-wave) - Waveform output by compare match(A/B per channel) - Captures counter value by input trigger 3-phase PWM wave generator for brushless DC motor - PWM output for chopper - Level output

SRAM IP

Remarkable Features of Renesas SRAM and TCAM IP. SRAM IP Portfolio ▪ Small area − By optimizing the peripheral circuit of memory, particularly small area is realized. ▪ Low power − Support low leak retention mode (Resume Standby) and power off mode (Shut down). ▪ IDM-oriented design quality

Embedded TCAM IP

KEY FEATURES OF TCAM - TCAM searches for data that matches the input value in one cycle from all information stored in the memory. - If there are multiple matching data, find all of them Also, by adding a priority encoder, it is possible to select one from multiple matching data. - The search

PCI Express 5.0 Link Controller

AMBA® AXI interface • Conforming to AMBA® AXI Protocol v1.0 Specification ARM IHI 0022B • Interface: Master/Slave • Endian: Little • Bus Width: 128 bits • DMAC functions are provided PCIe specification • Conforming to PCI Express Base Specification 5.0 • Supports PCIe1: 2.5[GT/s] PCIe2

Analog-PLL For Spread Spectrum Clock

・Including Loop-filter ・VCO operating range : 1600MHz - 3200MHz ・Output frequency range : 400MHz - 3200MHz ・Input frequency range : 10MHz - 200MHz ・Multiplying Output frequency / Input frequency : 2 - 320 ・Fractional multiplying available ・SSC function available -Modulation frequency: 20kH

Analog-PLL For Spread Spectrum Clock

・Including Loop-filter ・VCO operating range : 2000MHz - 4300MHz ・Output frequency range : 500MHz - 4300MHz ・Input frequency range : 10MHz - 200MHz ・Multiplying Output frequency / Input frequency : 2.5 - 430 ・Fractional multiplying available ・SSC function available -Modulation frequency : 2

Analog-PLL For Spread Spectrum Clock

▪ Including Loop-filter ▪ VCO operating range : 3000MHz - 6200MHz ▪ Output frequency range: 750MHz - 3100MHz ▪ Input frequency range: 10MHz - 200MHz ▪ Multiplying Output frequency / Input frequency : 3.75 - 620 ▪ Fractional multiplying available ▪ SSC function available − Modulation freque

ADPLL For Spread Spectrum Clock

▪ Supply voltage : min=0.81V, typ=0.9V, max=1.05V ▪ Operating temperature (Tj) : -40 - +125°C ▪ DCO frequency range : 900MHz - 3000MHz ▪ Output frequency range : 56.25MHz - 3000MHz ▪ Input frequency range : 8MHz - 192MHz ▪ Multiplying Output frequency / Input frequency : 0.293 - 375 ▪ Fract

Analog-PLL For Skew adjust

▪ Including Loop-filter ▪ VCO operating range : 560 - 1190 MHz ▪ Output frequency (CLKOUT): 40 - 1190 MHz ▪ Input frequency (CLKIN) : 10 - 170 MHz ▪ PFD comparison frequency : 10 - 85 MHz ▪ Multiplying CLKOUT / PFD : 14, 28 and 56 ▪ Divider − 4bit feedback divider (N divider) − 2bit input

32kHz Xtal Oscillator

▪ 32.768kHz, clock generation with crystal resonator ▪ External clock input mode(XOUT XBYP) is supported ▪ Not include the clock noise filter ▪ Power-down mode is supported ▪ Include the feedback resistor(Rfb) ▪ Rfb can be cut off. ▪ Not include the dumping resistor(Rd) and the internal cap

8 - 24 MHz Xtal Oscillator

▪ 8 - 24MHz, clock generation with crystal resonator. ▪ External clock input mode is supported. ▪ The clock noise filter is included. ▪ Power-down mode is supported. ▪ Include the feedback resistor(Rfb). ▪ Rfb can be cut off. ▪ Not include the dumping resistor(Rd) and the internal cap. ▪ At

12bit 2MSps A/D Converter

▪ Conversion method: Successive Approximation Register (SAR) ▪ Sampling rate: 2MSps(Max.) ▪ A/D clock frequency: 108 MHz ▪ Resolution: 12 bit ▪ DNL= -1LSB(Min.) / +2LSB(Max.) ▪ INL = -4LSB(Min.) / +4LSB(Max.） ▪ Analog supply voltage： VCCA = 1.8 ± 0.15 V ▪ Digital supply voltage: VDD = 0.9 ±

8bit 1Msps D/A Converter

▪ Resolution: 8bit ▪ monotonicity ▪ Accuracy: DNL ≤ +/-1LSB , INL ≤ +/-3LSB @ Rload = 2MΩ ▪ Conversion period：Settling time 1µs @ Cload = 20pF ▪ Sampling rate : 2Msps ▪ DAC enable control (saving the power consumption and releasing the IC terminal for other function) ▪ Analog supply voltage：

Temperature Sensor

▪ Power Supply − VCC(Analog)=1.7 ー 1.9V − VDD(Digital)=0.81 ー 1.05V ▪ Temperature Range : -40 ー 125℃ ▪ Relative Temperature Accuracy (*Note): -7 ー +7℃ *Note: 2 points calibration is needed every IP.

FPD-Link Receiver for TSMC 28nm HPC

▪ Renesas FPD-Link Receiver can be used for analog receiver of following interface . - ANSI/TIA/EIA-644※ ▪ Technology is TSMC 28nm HPC+ 1p10M ▪ Supply voltage can be applied 1.0V for overdrive of core voltage, 1.8V for IO voltage. ▪ With an input clock at 71.5MHz, the maximum data rate of each

FPD-Link Transmitter for TSMC 28nm HPC

▪ Renesas FPD-Link Transmitter can be used for analog transmitter of following interface . - ANSI/TIA/EIA-644 ▪ Technology is TSMC 28nm HPC 1p9M. ▪ Supply voltage can be applied 1.0V for overdrive of core voltage, 1.8V for IO voltage. ▪ With an input clock at 75MHz and input data at 150Mbps, t

FPD-Link Receiver for TSMC 22nm ULP

▪ Renesas FPD-Link Receiver can be used for analog receiver of following interface . - ANSI/TIA/EIA-644※ ▪ Technology is TSMC 22nm ULP 1p10M. ▪ Supply voltage can be applied 0.9V for voltage, 1.8V for IO voltage. ▪ With an input clock at 85MHz, the maximum data rate of each channel is 595Mbps.

FPD-Link Receiver for TSMC 22nm ULP

▪ Renesas FPD-Link Receiver can be used for analog receiver of following interface . - ANSI/TIA/EIA-644※ ▪ Technology is TSMC 22nm ULP 1p10M. ▪ Supply voltage can be applied 0.9V for voltage, 1.8V for IO voltage. ▪ With an input clock at 85MHz, the maximum data rate of each channel is 595Mbps.

FPD-Link Transmitter for TSMC 22nm ULP

▪ Renesas FPD-Link Transmitter can be used for analog transmitter of following interface . - ANSI/TIA/EIA-644 ▪ Technology is TSMC 22nm ULP 1p10M. ▪ Supply voltage can be applied 0.9V for core voltage, 1.8V for IO voltage. ▪ With an input clock at 75MHz and input data at 75Mbps, the maximum tr

USB2.0 PHY for TSMC 22nm ULL Single-Port Transceiver

Renesas USB2.0 Transceiver can be used for analog transceiver of following interface . - Universal Serial Bus Specification Revision 2.0 - Battery Charging Specification Revision 1.2 - Technology is TSMC 22nm ULL 1p9M (6x2r). - Supply voltage can be applied 1.1V for core voltage and 3.3V for I

USB2.0 Full-Speed Transceiver for TSMC 22nm ULL

Renesas USB2.0 FS Transceiver can be used for analog transceiver of following interface . - Universal Serial Bus Specification Revision 2.0 Full/Low-Speed - Technology is TSMC 40nm LP 1p9M (6x2r). - Supply voltage can be applied 1.1V for core voltage and 3.3V for IO voltage. - USB transfer mod

MIPI D-PHY Transmitter/Receiver for TSMC 22nm ULL

• Renesas MIPI D-PHY Transmitter/Receiver can be used for analog Transmitter/Receiver of following interface . - MIPI alliance Specification for D-PHY Version 2.1 15 December 2016. - MIPI alliance Specification for Display Serial Interface (DSI) Version 1.3.1 Aug 2015. - MIPI alliance Specific

MIPI D-PHY Receiver for TSMC 22nm ULP

• Renesas MIPI D-PHY Receiver can be used for analog Receiver of following interface . - MIPI alliance Specification for D-PHY Version 2.1 15 December 2016. - MIPI alliance Specification for Camera Serial Interface 2 (CSI-2) Version 2.0 7 Dec 2016. • Technology is TSMC 22nm ULP 1p10M. • Supply

MIPI CSI-2 Receiver IP Core

• Compliant with Specification for Camera Serial Interface 2 (CSI2 ®) Version 3.0. • Compliant with PHY Protocol Interface (PPI) to D-PHYTM Version 2.5. • Compliant with AMBA® APB Protocol Version 2.0. • Support PPI interface for D-PHY physical layer option. • Support Renesas original Vi

MIPI DSI-2 Transmitter IP Core

• Compliant with Specification for Display Serial Interface 2 (DSI-2 SM) Version 1.1. • Compliant with PHY Protocol Interface (PPI) to D-PHYSM Version 2.1. • Compliant with AMBA® APB Protocol Version 2.0. • Support PPI interface for D-PHY physical layer option • Support De-facto standard

MIPI D-PHY Transmitter/Receiver for Samsung 28nm FD-SOI

• Renesas MIPI D-PHY Transmitter/Receiver can be used for analog Transmitter/Receiver of following interface . - MIPI alliance Specification for D-PHY Version 2.1 15 December 2016. - MIPI alliance Specification for Display Serial Interface (DSI) Version 1.3.1 Aug 2015. - MIPI alliance Specific

MIPI D-PHY Transmitter/Receiver for TSMC 40nm LP

• Renesas MIPI D-PHY Transmitter/Receiver can be used for analog Transmitter/Receiver of following interface . - MIPI alliance Specification for D-PHY Version 2.1 15 December 2016. - MIPI alliance Specification for Display Serial Interface (DSI) Version 1.3.1 Aug 2015. - MIPI alliance Specific

32-bit RISC CPU IP

▪ 32-bit CPU + FPU, MMU option ▪ CPU with integrated vector FPU − 7MFLOPS / MHz ▪ Dual issue 32-bit CPU − 1.5DMIPS / MHz ▪ 5-stage pipeline

32-bit RISC CPU IP

▪ 32-bit internal data bus ▪ General-purpose register architecture: 16 32-bit general general-purpose registers − Register bank for fast interrupt response (15 banks) ▪ RISC type instruction set: Instruction length: 16 bits / 32 bits mixed, 16-bit basic instruction for improving code effici

SerDes PHY(PCIe3.0, USB3.1 SS) 10Gbps for TSMC 28nm HPC

▪ Renesas SerDes PHY can be used for analog transceiver of following interface. − PCI Express 3.0 / USB3.1 gen2 superspeed / Serial ATA 3.1/ 10GKR / SGMII *1 ▪ Multi-link support for area reduction in using multiple SerDes ▪ Technology is TSMC 28nm HPC+ 1p10M ▪ Supply voltage can be applied 0.

SerDes PHY(PCIe2.1, USB3.0 SS) 5Gbps for TSMC 28nm HPC

Renesas SerDes PHY can be used for analog transceiver of following interface . − PCI Express 2.1 ( compliant with “PCI-Express Base Specification Revision 2.1”) *1 − USB3.0 SuperSpeed ( compliant with “Universal Serial Bus 3.0 Specification Revision 1.0 ) *1 ▪ PCI Express 2.1 and USB3.0 SuperSp

USB2.0 PHY for TSMC 28nm HPC Multi-Port Transceiver

Renesas USB2.0 Transceiver can be used for analog transceiver of following interface . − Universal Serial Bus Specification Revision 2.0 *1 − Battery Charging Specification Revision 1.2 ▪ Supports Multi-port. ( 1 / 2 / 3 / 4 port type are available ) ▪ Technology is TSMC 28nm HPC+ 1p10M . ▪ S

USB2.0 PHY for Samsung 28nm Multi-Port Transceiver

Renesas USB2.0 Transceiver can be used for analog transceiver of following interface . − Universal Serial Bus Specification Revision 2.0 − Battery Charging Specification Revision 1.2 ▪ Supports Multi port. ( 1 or 2 port type are available ) ▪ Technology is Samsung 28nm FD SOI 8M . ▪ Supply vo

USB2.0 PHY for TSMC 40nm LP Single-Port Transceiver

Renesas USB2.0 Transceiver can be used for analog transceiver of following interface . − Universal Serial Bus Specification Revision 2.0 − Battery Charging Specification Revision 1.2 ▪ Technology is TSMC 40nm LP 1p7M/1p8M . ▪ Supply voltage can be applied 1.1V for core voltage and 3.3V for IO

Analog-PLL For Frequency Multiplying

▪ Including Loop-filter ▪ VCO operating range : 2000MHz - 4000MHz ▪ Output frequency range : 62.5MHz - 4000MHz ▪ Input frequency range : 20MHz - 200MHz ▪ Multiplying (Output freq. / PFD freq.) : 1.5625 - 200 ▪ Divider 7bit feedback divider, 3bit input divider and 3bit output divider ▪ 14bit

Analog-PLL For Spread Spectrum Clock

▪ ・Including Loop-filter ▪ ・VCO operating range : 900MHz - 1800 MHz ▪ ・Output frequency range : 900MHz – 1800 MHz ▪ ・Input frequency range : 12MHz - 192MHz ▪ ・Multiplying (Output freq. / PFD freq.) : 60 - 120 ▪ ・Divider 7bit feedback divider and 3bit input divider ▪ ・Power-down Mode ▪ ・Mul

Analog-PLL For Skew adjust

▪ Including Loop-filter ▪ VCO operating range : 672MHz - 1400 MHz ▪ Output frequency range : 48MHz – 1400 MHz ▪ Input frequency range : 12MHz - 400MHz ▪ Multiplying (Output freq. / PFD freq.) : 14, 28 and 56 ▪ Divider 4bit feedback divider, 2bit input divider and 4bit output divider ▪ Power

Analog-PLL For Frequency Multiplying

▪ Including Loop-filter ▪ VCO operating range : 850MHz - 1700 MHz ▪ Output frequency range : 850MHz – 1700 MHz ▪ Input frequency range : 9.6MHz - 216MHz ▪ Multiplying (Output freq. / PFD freq.) : 49 - 127 ▪ Divider 7bit feedback divider and 3bit input divider ▪ Power-down Mode ▪ Multiple o

Analog-PLL For Frequency Multiplying

▪ Including Loop-filter ▪ VCO operating range : 2500MHz - 5000MHz ▪ Output frequency range : 1250MHz - 2500MHz ▪ Input frequency range : 12MHz - 320MHz ▪ Multiplying (Output freq. / PFD freq.) : 64 - 127 ▪ Divider 7bit feedback divider and 3bit input divider ▪ Power-down Mode ▪ Multiple ou

Analog-PLL For Spread Spectrum Clock

▪ Including Loop-filter ▪ VCO operating range : 900MHz - 1800MHz ▪ Output frequency range : 900MHz – 1800MHz ▪ Input frequency range : 12MHz - 192MHz ▪ Multiplying (Output freq. / PFD freq.) : 60 - 120 ▪ Divider 7bit feedback divider and 3bit input divider ▪ Power-down Mode ▪ Multiple outp

Analog-PLL For Skew adjust

▪ Including Loop-filter ▪ VCO operating range : 720MHz - 1680MHz ▪ Output frequency range : 45MHz – 1680MHz ▪ Input frequency range : 22.528MHz - 420MHz ▪ Multiplying (Output freq. / PFD freq.) : 16 ▪ Divider 4bit feedback divider, 2bit input divider and 4bit output divider ▪ Power-down Mod

Analog-PLL For Frequency Multiplying

▪ Including Loop-filter ▪ VCO operating range : 580 -1250 MHz ▪ Output frequency range : 72.5 –1250 MHz ▪ Input frequency range : 9.6 -100MHz ▪ Multiplying (Output freq. / PFD freq.) : 40 -120 ▪ Divider -7bit feedback divider (N divider) -3bit input divider ( M divider ) ▪ Selectable feedbac

Analog-PLL For Spread Spectrum Clock

▪ Including Loop-filter ▪ VCO operating range : 640MHz - 1056 MHz ▪ Output frequency range : 80MHz – 1056 MHz ▪ Input frequency range : 10MHz - 132MHz ▪ Multiplying (Output freq. / PFD freq.) : 8 - 88 ▪ Divider 7bit feedback divider and 3bit input divider ▪ Power-down Mode ▪ Multiple outpu

Dual Channel 12b D/A Converter

▪ 12b resolution, 3µs conversion time ▪ Level Shifter inside. Directly connectable Interface to the digital section. ▪ Dual channel ▪ Independent Reference Voltage from the power supply ▪ Support 2 output mode; highly drivable mode / highly accurate mode. ▪ High Drivability of 50pF capacitive

Dual Channel 8b D/A Converter

▪ 8b resolution ▪ Dual Channel ▪ Ultra low Current consumption. ▪ 30µs conversion time with 1pF capacitive load ▪ Excellent Linearity ▪ suitable for the reference voltage generator for the comparators

12bit 2MSps SAR ADC

▪ Conversion method : Successive approximation ▪ Resolution : 12bit ▪ Conversion time : 0.5µs ▪ Differential nonlinearity : -1LSB(Min.)/+2LSB(Max.) ▪ Integral nonlinearity : -4LSB(Min.)/+4LSB(Max.) ▪ Supply voltage: VCCA=1.8+/-0.15V ▪ Analog Input range : 0 to VCCA, single-ended. ▪ 14ch ana

12bit 2.5MSps SAR ADC

▪ Conversion method : Successive approximation ▪ Resolution : 12/10/8bit selectable ▪ Conversion time : 0.4µs ▪ Differential nonlinearity : -1LSB(Min.)/+1LSB(Max.) ▪ Integral nonlinearity : -2LSB(Min.)/+2LSB(Max.) ▪ Supply voltage: VCCA=2.7 to 3.6 V ▪ Analog Input range : 0 to VREF, single-e

Temperature Sensor

▪ Temperature range : -40 to 125 °C ▪ Relative accuracy : +/-7 °C @ -40 to 80 °C, +/-6 °C @ 80 to 125 °C

Temperature Sensor

▪ Temperature range : -40 to 125 °C ▪ Relative accuracy : +/-0.5 °C @ -40 to 105 °C, +/-1 °C @ 105 to 125 °C (with 2 points calibration)

USB2.0 EHCI Host Controller IP Core I

General ▪ Compliant with Universal Serial Bus Specification Revision 2.0. ▪ Compliant with Enhanced Host Controller Interface(EHCI) Specification for USB Rev.1.1. ▪ Compliant with Open Host Controller Interface(OHCI) Specification for USB Rev.1.0a. ▪ Compliant with AMBA®3 AHB-Lite Protocol v1.

USB2.0 Peripheral Controller IP Core

General ▪ Compliant with Universal Serial Bus Specification Revision 2.0. ▪ Compliant with AMBA®3 AHB-Lite Protocol v1.0 Specification. ▪ Compliant with UTMI+ Specification Rev 1.0 Level-3. USB function ▪ Supports Control, Bulk, Interrupt and Isochronous transfers. ▪ Supports Battery Chargin

USB2.0 On-The-Go (OTG) Controller IP Core

General ▪ Compliant with Universal Serial Bus Specification Revision 2.0. ▪ Compliant with Enhanced Host Controller Interface(EHCI) Specification for USB Rev.1.1. ▪ Compliant with Open Host Controller Interface(OHCI) Specification for USB Rev.1.0a. ▪ Compliant with AMBA®3 AHB-Lite Protocol

USB3.1 Gen1 xHCI Host Controller IP Core

General ▪ Compliant with the Universal Serial Bus (USB) 3.1 Specification Revision 1.0. ▪ Compliant with the Universal Serial Bus Specification Revision 2.0. ▪ Compliant with the Battery Charging Specification Revision 1.2. ▪ Compliant with the PHY Interface for the CI Express, SATA, and USB3.

USB3.1 Gen1 Peripheral Controller IP Core

General ▪ Compliant with Universal Serial Bus 3.1 Specification Revision 1.0 ▪ Compliant with Universal Serial Bus Specification Revision 2.0 ▪ Compliant with PIPE3(PHY Interface for the PCI Express and USB3.0 Super Speed Architectures) Version 3.0 ▪ Compliant with USB2.0 Transceiver Macrocel

Configurable PCI Express 4.0 Link Controller

General - Compliant with “PCI Express Base Specification, Rev. 4.0 Version 1.0” - Compliant with “PHY Interface For the PCI Express, SATA, and USB3.1 Architectures” - Compliant with “AMBA® AXI Protocol Specification v1.0”