32-bit RISC CPU IP

▪32-bitinternaldatabus ▪Generalpurposeregisterfile: −1632-bitgeneral-purposeregisters (and832-bitshadowregisters) −Seven32-bitcontrolregisters −Four32-bitsystemregisters ▪RISCtypeinstructionset(withupward compatibilitywithSH-1,SH-2,SH-3,SH-4): −Instructi

Embedded TCAM IP

KEYFEATURESOFTCAM -TCAMsearchesfordatathatmatchestheinputvalueinonecyclefromallinformationstoredinthememory. -Iftherearemultiplematchingdata,findallofthem Also,byaddingapriorityencoder,itispossibletoselectonefrommultiplematchingdata. -Thesearch

PCI Express 5.0 Link Controller

AMBA®AXIinterface •ConformingtoAMBA®AXIProtocolv1.0 SpecificationARMIHI0022B •Interface:Master/Slave •Endian:Little •BusWidth:128bits •DMACfunctionsareprovided PCIespecification •ConformingtoPCIExpressBase Specification5.0 •Supports PCIe1:2.5[GT/s] PCIe2

MIPI D-PHY Transmitter/Receiver for TSMC 22nm ULL

•RenesasMIPID-PHYTransmitter/ReceivercanbeusedforanalogTransmitter/Receiver offollowinginterface. -MIPIallianceSpecificationforD-PHYVersion2.115December2016. -MIPIallianceSpecificationforDisplaySerialInterface(DSI)Version1.3.1Aug2015. -MIPIallianceSpecific

MIPI D-PHY Receiver for TSMC 22nm ULP

•RenesasMIPID-PHYReceivercanbeusedforanalogReceiveroffollowinginterface. -MIPIallianceSpecificationforD-PHYVersion2.115December2016. -MIPIallianceSpecificationforCameraSerialInterface2(CSI-2)Version2.07Dec2016. •TechnologyisTSMC22nmULP1p10M. •Supply

MIPI DSI-2 Transmitter IP Core

•CompliantwithSpecificationforDisplay SerialInterface2(DSI-2 SM)Version1.1. •CompliantwithPHYProtocolInterface (PPI)toD-PHYSMVersion2.1. •CompliantwithAMBA®APBProtocol Version2.0. •SupportPPIinterfaceforD-PHYphysical layeroption •SupportDe-factostandard

MIPI D-PHY Transmitter/Receiver for Samsung 28nm FD-SOI

•RenesasMIPID-PHYTransmitter/ReceivercanbeusedforanalogTransmitter/Receiver offollowinginterface. -MIPIallianceSpecificationforD-PHYVersion2.115December2016. -MIPIallianceSpecificationforDisplaySerialInterface(DSI)Version1.3.1Aug2015. -MIPIallianceSpecific

MIPI D-PHY Transmitter/Receiver for TSMC 40nm LP

•RenesasMIPID-PHYTransmitter/ReceivercanbeusedforanalogTransmitter/Receiver offollowinginterface. -MIPIallianceSpecificationforD-PHYVersion2.115December2016. -MIPIallianceSpecificationforDisplaySerialInterface(DSI)Version1.3.1Aug2015. -MIPIallianceSpecific

32-bit RISC CPU IP

▪32-bitCPU+FPU,MMUoption ▪CPUwithintegratedvectorFPU −7MFLOPS/MHz ▪Dualissue32-bitCPU −1.5DMIPS/MHz ▪5-stagepipeline

32-bit RISC CPU IP

▪32-bitinternaldatabus ▪General-purposeregisterarchitecture:16 32-bitgeneralgeneral-purposeregisters −Registerbankforfastinterrupt response(15banks) ▪RISCtypeinstructionset:Instructionlength: 16bits/32bitsmixed,16-bitbasic instructionforimprovingcodeeffici

SerDes PHY(PCIe3.0, USB3.1 SS) 10Gbps for TSMC 28nm HPC

▪RenesasSerDesPHYcanbeusedforanalogtransceiveroffollowinginterface. −PCIExpress3.0/USB3.1gen2superspeed/SerialATA3.1/10GKR/SGMII*1 ▪Multi-linksupportforareareductioninusingmultipleSerDes ▪TechnologyisTSMC28nmHPC+1p10M ▪Supplyvoltagecanbeapplied0.

SerDes PHY(PCIe2.1, USB3.0 SS) 5Gbps for TSMC 28nm HPC

RenesasSerDesPHYcanbeusedforanalogtransceiveroffollowinginterface. −PCIExpress2.1(compliantwith“PCI-ExpressBaseSpecificationRevision2.1”)*1 −USB3.0SuperSpeed(compliantwith“UniversalSerialBus3.0SpecificationRevision1.0)*1 ▪PCIExpress2.1andUSB3.0SuperSp

USB2.0 PHY for TSMC 28nm HPC Multi-Port Transceiver

RenesasUSB2.0Transceivercanbeusedforanalogtransceiveroffollowinginterface. −UniversalSerialBusSpecificationRevision2.0*1 −BatteryChargingSpecificationRevision1.2 ▪SupportsMulti-port.(1/2/3/4porttypeareavailable) ▪TechnologyisTSMC28nmHPC+1p10M. ▪S

USB2.0 PHY for Samsung 28nm Multi-Port Transceiver

RenesasUSB2.0Transceivercanbeusedforanalogtransceiveroffollowinginterface. −UniversalSerialBusSpecificationRevision2.0 −BatteryChargingSpecificationRevision1.2 ▪SupportsMultiport.(1or2porttypeareavailable) ▪TechnologyisSamsung28nmFDSOI8M. ▪Supplyvo

USB2.0 PHY for TSMC 40nm LP Single-Port Transceiver

RenesasUSB2.0Transceivercanbeusedforanalogtransceiveroffollowinginterface. −UniversalSerialBusSpecificationRevision2.0 −BatteryChargingSpecificationRevision1.2 ▪TechnologyisTSMC40nmLP1p7M/1p8M. ▪Supplyvoltagecanbeapplied1.1Vforcorevoltageand3.3VforIO

USB2.0 EHCI Host Controller IP Core I

General ▪CompliantwithUniversalSerialBusSpecificationRevision2.0. ▪CompliantwithEnhancedHostControllerInterface(EHCI)SpecificationforUSBRev.1.1. ▪CompliantwithOpenHostControllerInterface(OHCI)SpecificationforUSBRev.1.0a. ▪CompliantwithAMBA®3AHB-LiteProtocolv1.

USB2.0 Peripheral Controller IP Core

General ▪CompliantwithUniversalSerialBusSpecificationRevision2.0. ▪CompliantwithAMBA®3AHB-LiteProtocolv1.0Specification. ▪CompliantwithUTMI+SpecificationRev1.0Level-3. USBfunction ▪SupportsControl,Bulk,InterruptandIsochronoustransfers. ▪SupportsBatteryChargin

USB2.0 On-The-Go (OTG) Controller IP Core

General ▪CompliantwithUniversalSerialBusSpecification Revision2.0. ▪CompliantwithEnhancedHostController Interface(EHCI)SpecificationforUSBRev.1.1. ▪CompliantwithOpenHostController Interface(OHCI)SpecificationforUSBRev.1.0a. ▪CompliantwithAMBA®3AHB-LiteProtocol

USB3.1 Gen1 xHCI Host Controller IP Core

General ▪CompliantwiththeUniversalSerialBus(USB)3.1SpecificationRevision1.0. ▪CompliantwiththeUniversalSerialBusSpecificationRevision2.0. ▪CompliantwiththeBatteryChargingSpecificationRevision1.2. ▪CompliantwiththePHYInterfacefortheCIExpress,SATA,andUSB3.

USB3.1 Gen1 Peripheral Controller IP Core

General ▪CompliantwithUniversalSerialBus3.1SpecificationRevision1.0 ▪CompliantwithUniversalSerialBusSpecificationRevision2.0 ▪CompliantwithPIPE3(PHYInterfaceforthePCIExpressandUSB3.0SuperSpeedArchitectures) Version3.0 ▪CompliantwithUSB2.0TransceiverMacrocel

Configurable PCI Express 4.0 Link Controller

General -Compliantwith“PCIExpressBaseSpecification,Rev.4.0Version1.0” -Compliantwith“PHYInterfaceForthePCIExpress,SATA,andUSB3.1Architectures” -Compliantwith“AMBA®AXIProtocolSpecificationv1.0”

Ethernet AVB End Station

•FlowcontrolconformingwiththeIEEE802.3xstandard •TransmissionandreceptionofEthernet(IEEE802.3)frames •Supportstransferat100Mbpsand1000Mbps •SupportsinterfaceconformingtoIEEE802.3PHYGMIIandMII •SupportsIEEE802.1BA,IEEE802.1AS,IEEE802.1QavandIEEE1722functi

Ethernet TSN End Station

1.IntegratedEthernetCommunicationController(EthernetMAC)accordingtostandardIEEE802.3. 2.Thecontrollersupporttheseoperationmodes-10/100/1000Mbps-full-duplexoperation 3.PHYInterface:MII,RMII,GMII,RGMIIandSGMII(SGMIIisStandardVer1.8andusingExternalConverter) 4.

Ethernet TSN Layer 2/3 Switch

1.EthernetFramedatarouting/ForwardingusingVarioustransfersfeaturingadvancedfilters 2.IntegratedEthernetCommunicationController(EthernetMAC)accordingtostandardIEEE802.3intoeach Etherport 3.Thecontrollersupporttheseoperationmodes-10/100Mbps/1Gbps/2.5Gbps-full-d

32-bit RISC CPU

KeyFeatures RISCarchitecture 32-bitgeneralpurposeregisterx16 Numberofinstructions83 5stagepipeline Twoformatsof16bitlengthinstructionand32bitinstructionareadopted Thecodesizeoftheprogramcanbesuppressedbytheinstructionformatof16bit length