3.3-V DUAL PLL MULTICLOCK GENERATOR

FEATURES 27-MHz Master Clock Input Generated Audio System Clock (PLL1707): – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Generated Audio System Clock (PLL170

封装/外壳：20-SSOP（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC PLL MULTI-CLK GEN DUAL 20QSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

3.3 V DUAL PLL MULTICLOCK GENERATOR

文件：171.48 Kbytes Page：22 Pages

3.3-V DUAL PLL MULTICLOCK GENERATOR

文件：617.56 Kbytes Page：25 Pages

3.3-V DUAL PLL MULTICLOCK GENERATOR

FEATURES 27-MHz Master Clock Input Generated Audio System Clock (PLL1707): – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Generated Audio System Clock (PLL170

3.3-V DUAL PLL MULTICLOCK GENERATOR

文件：617.56 Kbytes Page：25 Pages

1 A, Low Dropout, CMOS Linear Regulator

GENERAL DESCRIPTION The ADP1706/ADP1707/ADP1708 are CMOS, low dropout linear regulators that operate from 2.5 V to 5.5 V and provide up to 1 A of output current. Using an advanced proprietary architecture, they provide high power supply rejection and achieve excellent line and load transient resp

Stock and Custom* Colors for Dome Plugs and Shorty Plugs

文件：89.88 Kbytes Page：1 Pages

AM1707 ARM Microprocessor

文件：1.31981 Mbytes Page：198 Pages

AM1707 ARM Microprocessor

文件：1.32968 Mbytes Page：198 Pages

ARM Microprocessor

文件：1.31119 Mbytes Page：199 Pages