1:5 Clock Distribution

Description The PI90LV14 implements low voltage differential signaling (LVDS) to achieve clocking rates as high as 320MHz with low skew. The PI90LV14 is a low-skew 1:5 clock distribution chip which incorporates multiplexed clock inputs to allow for distribution of a lower-speed, single-ended clo

1:5 Clock Distribution

Description The PI90LV14 implements low voltage differential signaling (LVDS) to achieve clocking rates as high as 320MHz with low skew. The PI90LV14 is a low-skew 1:5 clock distribution chip which incorporates multiplexed clock inputs to allow for distribution of a lower-speed, single-ended clo

1:5 Clock Distribution

Description The PI90LV14 implements low voltage differential signaling (LVDS) to achieve clocking rates as high as 320MHz with low skew. The PI90LV14 is a low-skew 1:5 clock distribution chip which incorporates multiplexed clock inputs to allow for distribution of a lower-speed, single-ended clo

封装/外壳：20-TSSOP（0.173"，4.40mm 宽） 包装：管件 描述：IC CLK BUFFER 2:5 250MHZ 20TSSOP 集成电路（IC） 时钟缓冲器，驱动器

封装/外壳：20-SSOP（0.154"，3.90mm 宽） 包装：管件 描述：IC CLK BUFFER 2:5 250MHZ 20QSOP 集成电路（IC） 时钟缓冲器，驱动器