Description

The PI90LV14 implements low voltage differential signaling (LVDS) to achieve clocking rates as high as 320MHz with low skew.

The PI90LV14 is a low-skew 1:5 clock distribution chip which incorporates multiplexed clock inputs to allow for distribution of a lower-speed, single-ended clock or a high-speed system clock. When LOWthe SEL pin will select the differential clock input.

Features

• Meets and Exceeds the Requirements of ANSI TIA/EIA-644-1995

• Designed for clocking rates up to 320MHz

• Operates from a single 3.3V Supply

• Low Voltage Differential Signaling (LVDS) with Output Voltages of ±350mV into a 100-ohm load

• Choice between LVDS or TTL clock input

• Synchronous Enable/Disable

• Clock outputs default LOW when inputs open

• Multiplexed clock input

― Internal 300kohms pullup resistor on input pins

― CLK & CLK have 110-ohm internal termination (PI90LVT14)

• 50ps Output-to-Output Skew

• 475ps typical propagation delay

• –22ps Period Jitter

• Bus Pins are high impedance when disabled or with VCC less than 1.5V

• TTL inputs are 5V Tolerant

• Power Dissipation at 400Mbits/s of 150mW

• Function compatible to Motorola (PECL)

― MC100EL14 and Micrel/Synergy (PECL)

― SY100EL14V

• >9kV ESD Protection

• 20-pin TSSOP (L) and QSOP (Q) packages