SMA Female to SMP Male Full Detent Adapter

文件：325.63 Kbytes Page：3 Pages

HIGH PERFORMANCE COMMUNICATION BUFFER Zero input - output delay

Description The ICS91305I is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at speeds f

HIGH PERFORMANCE COMMUNICATION BUFFER

Features • Zero input - output delay • Frequency range 10 - 133 MHz (3.3V) • 5V tolerant input REF • High loop filter bandwidth ideal for Spread Spectrum applications • Less than 200 ps Jitter between outputs • Skew controlled outputs • Skew less than 250 ps between outputs • Available in

HIGH PERFORMANCE COMMUNICATION BUFFER

Features • Zero input - output delay • Frequency range 10 - 133 MHz (3.3V) • 5V tolerant input REF • High loop filter bandwidth ideal for Spread Spectrum applications • Less than 200 ps Jitter between outputs • Skew controlled outputs • Skew less than 250 ps between outputs • Available in

HIGH PERFORMANCE COMMUNICATION BUFFER Zero input - output delay

Description The ICS91305I is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at speeds f

HIGH PERFORMANCE COMMUNICATION BUFFER Zero input - output delay

Description The ICS91305I is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at speeds f