丝印代码：-16；NPN resistor-equipped transistor

DESCRIPTION NPN resistor-equipped transistor FEATURES • Built-in bias resistors • Simplified circuit design • Reduction of component count • Reduced pick and place costs. APPLICATIONS • General purpose switching and amplification • Inverter and interface circuits • Circuit driver.

丝印代码：-16；NPN resistor-equipped transistor; R1 = 10 kohm, R2 = 10 kohm

DESCRIPTION NPN resistor-equipped transistor FEATURES • Built-in bias resistors • Simplified circuit design • Reduction of component count • Reduced pick and place costs. APPLICATIONS • General purpose switching and amplification • Inverter and interface circuits • Circuit driver.

丝印代码：-16；NPN resistor-equipped transistor; R1 = 10 k廓, R2 = 10 k廓

丝印代码：16；50 V, 100 mA NPN resistor-equipped transistor; R1 = 10 kΩ, R2 = 10 kΩ

1. General description NPN Resistor-Equipped Transistor (RET) in a small SOT23 Surface-Mounted Device (SMD) plastic package. PNP complement: PDTA114ET 2. Features and benefits • 100 mA output current capability • Built-in bias resistors • Simplifies circuit design • Reduces component cou

丝印代码：16；NPN resistor-equipped transistors; R1 = 10 k, R2 = 10 k

Features and benefits  100 mA output current capability  Built-in bias resistors  Simplifies circuit design  Reduces component count  Reduces pick and place costs  AEC-Q101 qualified

Digital Transistor(NPN)

Features « Built bias resistors « making device design easy « almost completely eliminating parasitic effects

NPN resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ

丝印代码：-16；NPN resistor-equipped transistors; R1 = 10 k?? R2 = 10 k?

丝印代码：-16；NPN resistor-equipped transistors

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丝印代码：-16；Low VCEsat (BISS) transistors

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丝印代码：16；50 V, 100 mA NPN resistor-equipped transistor; R1 = 10 kΩ, R2 = 10 kΩ

1. General description NPN Resistor-Equipped Transistor (RET) in a small SOT23 Surface-Mounted Device (SMD) plastic package. PNP complement: PDTA114ET-Q 2. Features and benefits • 100 mA output current capability • Built-in bias resistors • Simplifies circuit design • Reduces component c

封装/外壳：TO-236-3，SC-59，SOT-23-3 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：TRANS PREBIAS NPN 250MW TO236AB 分立半导体产品 晶体管 - 双极（BJT）- 单，预偏置

封装/外壳：TO-236-3，SC-59，SOT-23-3 包装：剪切带（CT）带盒（TB） 描述：TRANS RET TO-236AB 分立半导体产品 晶体管 - 双极（BJT）- 单，预偏置

50 V, 100 mA NPN resistor-equipped transistor; R1 = 10 kΩ, R2 = 10 kΩ

PNP SILICON BIAS RESISTOR TRANSISTOR

This new series of digital transistors is designed to replace a single device and its external resistor bias network. The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base–emitter resistor. The

Bias Resistor Transistor PNP Silicon Surface Mount Transistor with Monolithic Bias Resistor Network

The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base–emitter resistor. These digital transistors are designed to replace a single device and its xternal resistor bias network. The BRT eliminate

CASE 463-01, STYLE 1 SOT-416/SC-90

The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base–emitter resistor. These digital transistors are designed to replace a single device and its external resistor bias network. The BRT eliminat

CASE 463-01, STYLE 1 SOT-416/SC-90

Bias Resistor Transistor NPN Silicon Surface Mount Transistor with Monolithic Bias Resistor Network The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base–emitter resistor. These digital trans

0.25關m Sea of Gates and Customer Structured Arrays

DESCRIPTION Oki’s 0.25µm Application-Specific Integrated Circuit (ASIC) products are available in both Sea Of Gates (SOG) and Customer Structured Array (CSA) architectures. Both the SOG-based MG115P series and the CSA-based MG75P series use a five-layer metal process on 0.25µm drawn (0.18µm L-eff